Copy Instruction Scheduling for Software Pipelined Loops
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Solution Overview
Problem
Software pipelining of loops is constrained by register dependencies, leading to increased initiation intervals and inefficiencies due to the introduction of copy instructions, particularly in static single assignment form code, which can result in incorrect execution or inefficiency.
Innovation Solution
A method and apparatus for predicting and scheduling copy instructions in software pipelined loops by identifying register dependencies and inserting copy instructions to maintain correct register values, determining new initiation intervals, and selecting optimal schedules to minimize the impact of copy instructions on execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If software pipelining is applied to maximize instruction level parallelism, then execution speed is improved, but register dependencies between iterations cause incorrect execution or require increased initiation intervals
Solution Approach 1:
The patent applies preliminary action by performing modulo scheduling analysis before code generation to predict and identify all copy instructions that will be required. This advance planning allows the compiler to insert the necessary copy instructions into the scheduled code, ensuring correct register value propagation across loop iterations while maintaining the optimized initiation interval. The copy instructions are placed at precise locations determined by the modulo schedule, preventing incorrect execution while preserving parallelism.
2Reliability
If copy instructions are inserted to maintain correct register values, then execution correctness is improved, but initiation interval increases and performance decreases
Solution Approach 1:
The patent performs preliminary analysis through modulo scheduling to identify exactly where copy instructions are needed and when they will be executed. This allows the compiler to insert copy instructions at optimal locations that maintain correctness while minimizing their impact on the initiation interval. By knowing in advance which copies are necessary and when they will be issued, the compiler can avoid unnecessary copies and ensure that critical path operations are not delayed.
Solution Approach 2:
The patent changes the parameter of initiation interval from a fixed value determined by naive software pipelining to an optimized value derived from modulo scheduling analysis. The modulo schedule provides a systematic way to determine the minimum initiation interval that accommodates all data dependencies, including those requiring copy instructions. This parameter optimization ensures that the loop executes as fast as possible while maintaining correctness.
3Productivity
If initiation interval is reduced to increase pipelining, then instruction level parallelism is improved, but the likelihood of register value conflicts increases
Solution Approach 1:
The patent applies preliminary action by performing modulo scheduling analysis to determine the minimum safe initiation interval before generating code. This analysis examines all loop instructions and their dependencies to identify exactly when copy instructions are needed to preserve register values across iterations. By planning ahead, the compiler can set an aggressive (low) initiation interval while still ensuring correctness, because it knows precisely where copy operations will occur and will not conflict with other instructions.
Solution Approach 2:
The patent uses copy instructions as intermediary operations to transfer register values from one iteration to the next when needed. These copy instructions act as mediators that resolve potential conflicts between iterations, allowing the loop to maintain a low initiation interval. The copy instructions are inserted at specific points in the modulo schedule where they capture register values before they would be overwritten, ensuring that subsequent iterations can safely use the same physical registers.
Data Source
AI summary
A method for scheduling instructions for execution on a computer system includes scanning a plurality of loop instructions that are modulo scheduled to identify a first instruction and a second instruction that both utilize a register of the computer system upon execution of the plurality of instructions. The loop has a first initiation interval. The first instruction defines a first value of the register in a first iteration of the loop and the second instruction redefines the value of the register to a second value in a subsequent iteration of the loop prior to a use of the first value in the first iteration of the loop. A copy instruction is inserted in the loop instructions to copy the first value prior to execution of the second instruction. A schedule is determined after the insertion of the one or more copy instructions giving a second initiation interval.