Copy-Paste Memory Move Instructions for RISC Register Pressure
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Solution Overview
Problem
In RISC processor architectures, memory moves consume architected registers for an extended duration, leading to inefficiencies and decreased performance due to the need for load-store instruction pairs, which limits the availability of these scarce resources for other instructions.
Innovation Solution
Implementing a copy-paste functionality with a processor core that uses a store-through upper level cache and a store-in lower level cache, where copy-type and paste-type instructions manage data granules in non-architected buffers, reducing the pressure on architected registers by allowing simultaneous use during memory moves.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If load-store instruction pairs are used to move data in RISC architecture, then data can be moved between system memory locations, but architected registers are occupied for extended intervals reducing throughput
Solution Approach 1:
The patent introduces a buffer as an intermediary component between the processor core and system memory. The buffer temporarily holds data during memory move operations, allowing the processor to issue multiple copy-type and paste-type instructions without occupying architected registers for the entire duration of data transfer. This intermediary buffer resolves the contradiction by decoupling the register occupation time from the actual data movement time.
Solution Approach 2:
The patent segments the memory move operation into multiple independent copy-type and paste-type instructions that can be interleaved with other operations. Instead of a single load-store pair that occupies registers continuously, the data movement is divided into discrete copy operations (loading data to buffer) and paste operations (storing from buffer), which can be executed in a pipelined manner with other instructions.
2Productivity
If architected registers are allocated for memory move operations, then data can be transferred between memory locations, but the scarce register resources become unavailable for other instructions
Solution Approach 1:
The buffer serves as a mediator that absorbs the data holding requirement during memory moves. By placing data in the buffer rather than in architected registers, the register file remains available for other instructions while the buffer maintains the data for subsequent paste operations. This resolves the resource contention between memory move operations and other instructions.
Solution Approach 2:
The patent creates a copy of the data in the buffer, allowing the original data to remain in system memory while a duplicate is held in the buffer for paste operations. This copying mechanism eliminates the need to hold data in expensive architected registers, as the buffer provides sufficient temporary storage capacity for the data movement operation.
3Quantity of substance
If multiple load-store instruction pairs are executed sequentially for memory moves, then large data sets can be transferred, but processor performance decreases due to extended register occupation
Solution Approach 1:
The patent segments large data set transfers into multiple independent copy-paste instruction pairs that can be executed in an interleaved, pipelined fashion. Each copy-type instruction loads a data granule to the buffer, and each paste-type instruction stores a data granule from the buffer, creating multiple instruction-level parallelism opportunities that improve overall processor performance while transferring large volumes of data.
Solution Approach 2:
The buffer enables continuous data movement operations by maintaining data availability for paste operations even when copy operations are in progress or when other instructions are executing. This continuity eliminates idle cycles in the processor pipeline, allowing useful work to continue throughout the entire data transfer process rather than stopping for register availability.
Data Source
AI summary
A processor core has a store-through upper level cache and a store-in lower level cache. In response to execution of a memory move instruction sequence including a plurality of copy-type instruction and a plurality of paste-type instructions, the processor core transmits a corresponding plurality of copy-type and paste-type requests to the lower level cache, where each copy-type request specifies a source real address and each paste-type request specifies a destination real address. In response to receipt of each copy-type request, the lower level cache copies a respective one of a plurality of data granules from a respective storage location specified by the source real address of that copy-type request into a non-architected buffer. In response to receipt of each paste-type request, the lower level cache writes a respective one of the plurality of data granules from the non-architected buffer to a respective storage location specified by the destination real address of that paste-type request.