Fast CORDIC Envelope Tracking for LTE RF Modulation

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Solution Overview

Problem

Traditional envelope tracking systems generate envelope signals that are not fast or accurate enough for the LTE standard, particularly requiring a digital sampling clock of 104 MHz for 20 MHz LTE bandwidth, necessitating a method to generate fast digital envelope signals using in-phase and quadrature signals for RF modulation.

Innovation Solution

A coordinate rotation digital computer (CORDIC) is employed to compute the norm of vectors by rotating them onto a quadrant axis using an array of unit vectors, with each rotator stage multiplying the vector components by cosine and sine coefficients to achieve efficient vector processing, enabling high-rate vector calculations suitable for RF modulation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If traditional envelope tracking methods are used, then device complexity is reduced, but processing speed and accuracy are insufficient for LTE standards requiring 104 MHz sampling clock

Engineering Contradiction:
Improveprocessing speedVSAvoiddevice complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The CORDIC algorithm divides the vector rotation operation into multiple discrete stages, each handling a specific rotation angle. The rotator is segmented into N stages where each stage performs a fixed rotation, allowing parallel processing and achieving high-speed operation at 104 MHz sampling rate required for LTE standards.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The algorithm pre-calculates and stores rotation coefficients (tangent values) in lookup tables before execution. This preliminary preparation of trigonometric values enables the rotator to perform rapid vector transformations without real-time computation of complex trigonometric functions, significantly improving processing speed.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If digital sampling clock frequency is increased to 104 MHz for 20 MHz LTE bandwidth, then envelope signal accuracy is improved, but processing complexity and computational load increase

Engineering Contradiction:
Improveenvelope signal accuracyVSAvoidcomputational complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent replaces complex real-time trigonometric computation with a streamlined digital signal processing approach using CORDIC iteration. This substitution uses simple arithmetic operations (additions and bit shifts) instead of computationally intensive sine and cosine calculations, achieving high precision envelope tracking at 104 MHz without excessive computational burden.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The algorithm transforms the problem from calculating vector norms using square roots and trigonometric functions to an iterative rotation process that converges to the solution through parameter updates. By changing the mathematical approach from direct calculation to iterative approximation, the system achieves high accuracy while reducing computational complexity suitable for high-speed operation.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8782107B2Digital fast CORDIC for envelope tracking generation
Publication Date: 2014.07.15 QORVO US INC
  • US8782107B2 patent drawing
  • US8782107B2 patent drawing
  • US8782107B2 patent drawing

AI summary

Disclosed is a coordinate rotation digital computer (CORDIC) having a maximum value circuit that selects a larger of the first component or the second component. A minimum value circuit selects a minimum operand that is a smaller one of the first component or the second component. Also included are N rotator stages, each corresponding to a unique one of N predetermined vectors, each of the N rotator stages having a first multiply circuit to multiply the maximum operand by a cosine coefficient of a predetermined vector to output a first rotation component, a second multiply circuit for multiplying the minimum operand by a sine coefficient of the predetermined vector to output a second rotation component, and an adder circuit for adding the first rotation component to the second rotation component to output one of N results, and a maximum value circuit for outputting a maximum one of the N results.