N-Stage CORDIC Processor Macro-Iteration Control
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Solution Overview
Problem
Existing CORDIC processors are inflexible and inefficient when adapted for different applications and data characteristics, and they occupy more space on integrated circuits compared to specialized signal processors.
Innovation Solution
A custom N-stage CORDIC processor is designed for programmable logic arrays, incorporating a counter for macro-iterations and a multiplexer to select inputs or outputs, allowing for flexible operation and reduced size through pipelining and cascading of CORDIC engines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a general custom-designed signal processor is used, then it can perform various signal processing functions, but it operates slower and takes up more real estate on an integrated circuit
Solution Approach 1:
The CORDIC processor is divided into multiple stages (N-stage CORDIC processor) that can be pipelined. Each stage processes a portion of the computation, allowing parallel processing and improving overall speed while maintaining the ability to perform various trigonometric and hyperbolic calculations through configurable parameters.
Solution Approach 2:
The processor incorporates a counter that counts M macro-iterations and controls the operation cycles dynamically. The system can adapt its operation mode (micro-iterations vs macro-iterations) based on computational requirements, optimizing between speed and precision for different signal processing tasks.
2Adaptability or versatility
If a general custom-designed signal processor is used, then it can perform various signal processing functions, but it takes up more real estate on an integrated circuit
Solution Approach 1:
The CORDIC processor is designed as a universal computational engine that can perform multiple types of calculations (trigonometric functions, hyperbolic functions, linear calculations) through a single unified architecture. By configuring the N-stage processor with different iteration counts and parameter settings, the same hardware circuit accomplishes diverse signal processing functions, reducing the need for multiple specialized circuits.
Solution Approach 2:
The processor implements nested iteration structures where M macro-iterations contain N micro-iterations each. This hierarchical nesting allows the system to achieve high computational precision through multiple refinement passes while reusing the same hardware resources repeatedly, minimizing the overall circuit area required.
3Measurement precision
If more iteration cycles are performed, then calculation precision is improved, but processing time increases
Solution Approach 1:
The counter dynamically controls the number of macro-iterations (M) and micro-iterations (N) based on the specific computational task requirements. For simple calculations, fewer iterations are performed for faster results; for complex calculations requiring higher precision, the counter enables additional iteration cycles. This dynamic adjustment optimizes the trade-off between precision and processing time.
Solution Approach 2:
The processor uses periodic iteration cycles structured in macro-iterations, where each macro-iteration consists of N micro-iterations. This periodic structure allows the system to accumulate precision incrementally over multiple cycles while maintaining a regular, predictable timing pattern that facilitates efficient pipeline processing and resource utilization.
Data Source
AI summary
A CORDIC engine includes an N-stage CORDIC processor for performing N micro-iterations of a CORDIC algorithm and generating a 3-vector CORDIC output responsive to a 3-vector CORDIC input. A counter counts a number of M macro-iterations for the CORDIC algorithm and indicates a start of the cycle iterations. A multiplexer selects an input to the N-stage CORDIC processor as the 3-vector CORDIC input at the start of the cycle iterations or the 3-vector CORDIC output at other times. The CORDIC algorithm is complete after N*M clock cycles by generating N micro-iterations for each of the M macro-iterations. In some embodiments, the CORDIC engine is coupled to programmable logic blocks as part of a programmable logic array.