Core Address Register for Direct Test Access in Multi-Core Systems
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing test access protocols for multiple core systems, such as JTAG, incur overhead by requiring serial scanning through all TAP chains to communicate with a single core, which is inefficient and costly due to the need for bypassing non-addressed cores.
Innovation Solution
A test access protocol machine with a core address register and a signal routing control circuit allows direct addressing and routing of output test data from a selected computational core, enabling efficient communication without serial scanning through additional cores by using logical AND gates and multiplexers to control test clock access and data routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If JTAG serial scan protocol is used to access multiple cores, then all cores can be tested through a single TAP chain, but the overhead increases due to serial scanning through all cores including non-addressed ones
Solution Approach 1:
The patent segments the TAP chain into independent core-level TAP chains by introducing core-level TAP controllers. Each core has its own TAP controller that can be independently activated, allowing the test access to be divided into parallel operations rather than a single serial scan through all cores.
Solution Approach 2:
The patent implements dynamic activation of TAP controllers at the core level. The test access protocol dynamically selects which core's TAP controller to activate based on the target core address, enabling flexible and efficient access to specific cores without scanning through all cores in sequence.
2Length of stationary object
If non-addressed cores are placed in bypass mode to minimize TAP chain length, then the total TAP chain length is reduced, but overhead cost increases due to the bypass mode requirement
Solution Approach 1:
The patent extracts the TAP controller function from the core-level interface and implements it as a separate, activatable module. This allows the TAP controller to be selectively enabled only for the target core during testing, removing the need for all cores to remain in the TAP chain simultaneously and eliminating the bypass mode overhead.
Solution Approach 2:
The patent performs preliminary configuration by loading the target core address into the core address register before initiating the test access sequence. This preliminary action enables the signal routing control circuit to pre-determine the correct core's TAP controller to activate, avoiding unnecessary scanning and bypass operations.
3Adaptability or versatility
If traditional JTAG TAP chain architecture is used, then compatibility with existing standards is maintained, but efficient direct access to individual cores cannot be achieved
Solution Approach 1:
The patent makes the core-level TAP controller universal by designing it to handle both standard JTAG test access operations and the enhanced direct access functionality. The same TAP controller architecture supports both modes of operation, maintaining JTAG compatibility while enabling efficient individual core access through the additional core address register and signal routing control circuit.
Data Source
AI summary
An electronic circuit includes multiple computational cores. A test access protocol machine with a core address register and a signal routing control circuit addresses a selected computational core as specified by the core address register and routes output test data from the selected computational core.