Hardware Core Availability Notifications for Dynamic Thread Affinitization
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Solution Overview
Problem
Multi-processor computer systems face performance degradation due to power or thermal constraints, where some processor cores become inactive, leading to incorrect scheduling and resource allocation by software components that are unaware of the core availability changes.
Innovation Solution
Hardware circuitry identifies power, thermal, or scalability constraints and notifies the operating system to place specific cores into a forced idle state, allowing the OS to inform software applications and drivers, enabling dynamic adjustment of thread counts and affinitization based on available cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If power controller reduces capabilities by lowering frequency and/or voltage during power or thermal constraints, then power consumption and thermal conditions are improved, but processing performance deteriorates
Solution Approach 1:
The processor is segmented into multiple independent cores, allowing the power controller to selectively reduce capabilities of specific cores rather than uniformly reducing all cores' frequency and voltage. This segmentation enables partial performance maintenance while managing power consumption.
Solution Approach 2:
Different cores are assigned different operational states based on local conditions - some cores remain active at full performance while others are placed in forced idle state. This local quality approach allows the system to maintain processing performance in critical areas while reducing power consumption in less critical areas.
2Use of energy by stationary object
If power controller places certain cores into inactive state to resolve power or thermal conditions, then power consumption is reduced, but performance deteriorates particularly for workloads affinitized to inactive cores
Solution Approach 1:
A notification mechanism provides feedback from the power controller to software components about which cores are in forced idle state. This feedback enables software to dynamically adjust thread counts and affinitization, preventing workloads from being assigned to inactive cores and thereby maintaining overall workload execution performance while still achieving power reduction benefits.
Solution Approach 2:
The system dynamically adjusts the number of active cores based on power and thermal conditions, allowing the core availability to change over time. Software components can respond to these dynamic changes by adjusting their threading behavior, ensuring optimal performance under varying operational conditions.
3Ease of operation
If software components assume all cores are available for scheduling, then scheduling simplicity is maintained, but incorrect scheduling occurs leading to performance degradation
Solution Approach 1:
The power controller acts as an intermediary between the hardware core availability status and software scheduling decisions. By providing notifications about forced idle cores, it enables software to make informed scheduling decisions without requiring complex hardware monitoring, thus maintaining scheduling simplicity while improving workload execution efficiency.
Data Source
AI summary
In one embodiment, a processor includes: a plurality of cores to execute instructions; at least one monitor coupled to the plurality of cores to measure at least one of power information, temperature information, or scalability information; and a control circuit coupled to the at least one monitor. Based at least in part on the at least one of the power information, the temperature information, or the scalability information, the control circuit is to notify an operating system that one or more of the plurality of cores are to transition to a forced idle state in which non-affinitized workloads are prevented from being scheduled. Other embodiments are described and claimed.