Core Board Recess Layout for Accurate Embedded Chip Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor packaging methods face issues with misalignment and skewing of semiconductor chips due to the formation of openings in the core board, leading to poor electrical connections and reliability problems.
Innovation Solution
The method involves forming misaligned and unpenetrated recessed portions on both sides of the core board to accommodate electronic elements, ensuring accurate alignment of the elements with blind holes and conductive vias, thereby improving electrical connections and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If an opening is formed in the core board to place the semiconductor chip, then the chip can be embedded to reduce device size, but the dielectric layer will impact the chip and cause misalignment or skew
Solution Approach 1:
The opening is divided into two separate recessed portions: a first recessed portion on the first side of the core board and a second recessed portion on the second side. This segmentation allows the chip to be properly positioned without the dielectric layer causing misalignment, as the recessed portions provide dedicated spaces that prevent impact and skew during the filling process.
2Reliability
If the opening depth is greater than the chip thickness, then the chip can be fully embedded, but the dielectric layer will cause the chip to shift or skew
Solution Approach 1:
The recessed portions are formed in advance in the core board before the dielectric layer is applied. By pre-preparing these recessed spaces at the correct depth and position, the chip is already positioned properly before the dielectric layer fills the opening, preventing any subsequent shift or skew that would compromise alignment precision.
3Length of moving object
If the chip is embedded in the package substrate, then the overall device size is reduced, but alignment accuracy between electrode pads and blind holes deteriorates
Solution Approach 1:
The embedding structure is segmented into two separate recessed portions on opposite sides of the core board. This segmentation allows the chip to be securely positioned in the first recessed portion while the second recessed portion accommodates the dielectric layer without causing skew, thereby maintaining accurate alignment between the electrode pads and the blind holes even though the chip is embedded.
Data Source
AI summary
An electronic package and a manufacturing method thereof are provided, in which a first recessed portion and a second recessed portion are respectively formed on a first side and a second side of a core board, a first electronic element and a second electronic element are respectively disposed in the first recessed portion and the second recessed portion, an insulating layer fills the first recessed portion and the second recessed portion to cover the first electronic element and the second electronic element, a circuit layer is formed on the insulating layer, and a plurality of conductive blind vias are formed in the insulating layer and electrically connected to the circuit layer as well as the first and second electronic elements, so that the first electronic element and the second electronic element will not offset when the insulating layer fills the first recessed portion and the second recessed portion.