Core-Cache Cluster Aggregation for Multi-Core Processor Scalability

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Solution Overview

Problem

Multi-core processors face scalability issues due to system interconnect latency and interconnect saturation as the number of processor cores increases, leading to performance degradation in centralized and distributed cache architectures.

Innovation Solution

A scalability agent protocol that aggregates core-cache clusters, managing memory coherency and appearing as a single caching agent to the system interconnect, while maintaining low cache latency and distributing workload evenly among clusters, thus mitigating interconnect saturation and allowing for flexible scalability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the number of processor cores is increased to improve processing capability, then multi-threading performance is improved, but system interconnect latency increases and interconnect saturation occurs

Engineering Contradiction:
Improvemulti-threading performanceVSAvoidsystem interconnect latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The system is segmented into multiple independent core-cache clusters, where each cluster operates autonomously with its own private cache. This segmentation reduces interconnect traffic by keeping data local to clusters, thereby maintaining low latency even as the total number of cores increases.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A scalability agent is introduced as an intermediary component that manages communication between core-cache clusters. The scalability agent handles inter-cluster transactions, aggregates cache responses, and presents a unified interface to the system interconnect, reducing interconnect saturation by consolidating communication paths.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If more processor cores are added to the same IC to improve processing capability, then multi-threading capabilities are enhanced, but interconnect saturation and scalability issues occur

Engineering Contradiction:
Improvemulti-threading capabilitiesVSAvoidinterconnect saturation
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The processor is divided into multiple core-cache clusters that can be independently configured and scaled. Each cluster maintains its own cache hierarchy, segmenting the memory subsystem to reduce interconnect traffic and avoid saturation as more cores are added.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The scalability agent provides universal functionality by handling various types of inter-cluster transactions (read, write, invalidate) and presenting a unified caching interface to the system interconnect regardless of the number of clusters, simplifying the interconnect interface while supporting scalability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If core-cache clusters are aggregated to form larger processors to improve processing capability, then flexibility and scalability are enhanced, but maintaining memory coherency across clusters becomes complex

Engineering Contradiction:
ImprovescalabilityVSAvoidmemory coherency management
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The scalability agent acts as a mediator that manages memory coherency across core-cache clusters. It implements cache coherence protocols, tracks shared data, and coordinates access between clusters, centralizing coherency management to simplify the overall system architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The scalability agent implements feedback mechanisms by monitoring cache states across clusters, detecting coherence violations, and initiating appropriate coherence actions (invalidate, share, exclusive). This feedback loop maintains memory coherency automatically as clusters are dynamically aggregated or separated.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8028131B2System and method for aggregating core-cache clusters in order to produce multi-core processors
Publication Date: 2011.09.27 TAHOE RES LTD
  • US8028131B2 patent drawing
  • US8028131B2 patent drawing
  • US8028131B2 patent drawing

AI summary

According to one embodiment of the invention, a processor comprises a memory, a plurality of processor cores in communication with the cache memory and a scalability agent unit that operates as an interface between an on-die interconnect and both multiple processor cores and memory.