Core Capping Film and Contact Etching for Cell-Core Planarity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The miniaturization of semiconductor circuit patterns leads to challenges in the manufacturing process, particularly due to the protruding shape of bit lines which causes a step difference between the cell and core areas, making it difficult to secure a process margin and complicating subsequent processes like wiring.
Innovation Solution
A method of fabricating a semiconductor device that involves defining cell and core areas, forming bit line and gate structures, and using a core capping film with a greater height than the bit line structure. This method includes forming contact films, etching them to specific heights, and using a mask to expose the core capping film, thereby ensuring an etching rate that is greater for the contact films than for the bit line and core capping films.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If bit lines are formed with a protruding shape to accommodate miniaturized circuit patterns, then the circuit integration density is improved, but a step difference is generated between the cell area and core area
Solution Approach 1:
The patent applies local quality by forming a core capping film specifically in the core area to compensate for the step difference, while leaving the cell area bit line structure unchanged. This localized approach addresses the height discrepancy only where needed, maintaining the protruding bit line shape in the cell area for high integration density while creating a planar surface in the core area for subsequent processing.
Solution Approach 2:
The core capping film is formed in advance before subsequent wiring and contact formation processes. This preliminary action of elevating the core area surface allows subsequent layers to be formed without being affected by the underlying step difference, ensuring process margin and preventing pattern defects in later stages.
2Manufacturing precision
If the bit line structure is maintained with its original height, then the circuit pattern miniaturization is achieved, but the process margin for the cell area and core area is reduced
Solution Approach 1:
The solution applies local quality by selectively forming the core capping film only in the core area, leaving the cell area bit line structure at its original miniaturized height. This localized compensation maintains manufacturing precision in the cell area while providing process margin in the core area where the capping film creates a planar reference surface.
3Shape
If a planarization process is used to eliminate the step difference, then the surface flatness is improved, but the device complexity and process steps are increased
Solution Approach 1:
The patent extracts the planarization function from a general CMP process and implements it specifically through the core capping film formation. Instead of applying a complex multi-step CMP process across the entire wafer, the solution isolates the planarization need to the core area and addresses it with a targeted capping film deposition, reducing overall process complexity.
Solution Approach 2:
The core capping film acts as an intermediary layer that provides the planarization function. Rather than directly removing material through CMP to achieve flatness, the capping film serves as a mediator that compensates for the step difference, creating a planar surface for subsequent processing without requiring aggressive material removal.
4Productivity
If the etching rate for the contact film is increased to match the bit line structure height, then the contact film formation speed is improved, but pattern defects may occur in the core area
Solution Approach 1:
The patent applies local quality by having different etching rates for different areas: a higher etching rate in the cell area to match the bit line structure height for efficient contact formation, and a lower etching rate in the core area protected by the capping film to prevent pattern defects. This spatially differentiated etching approach maintains productivity while ensuring reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach eliminates the step difference between the bit line structures and the core capping film, securing a process margin for both areas and facilitating subsequent processes such as wiring, while also enhancing the reliability of the semiconductor device by preventing pattern defects.
Implementation Method 1
etching the first contact film until a height of the first contact film is less than that of the bit line structure using an etching process. The etching rate for the first contact film is greater than the etching rates for the bit line structure and the core capping film
Data Source
AI summary
A method of fabricating a semiconductor device. A cell area and a core area are defined in a substrate. A bit line structure disposed in the cell area is provided. A gate structure disposed in the core area is provided, and a core capping film disposed on the gate structure is provided. A height of the core capping film is greater than a height of the bit line structure. A first contact film is formed on the bit line structure. A second contact film is formed on the core capping film. A mask is formed on the first contact film. An upper surface of the core capping film is exposed using the mask. The first contact film is etched until a height of the first contact film becomes less than a height of the bit line structure using an etching process. In the etching process, an etching rate for the first contact film is greater than etching rates for the bit line structure and the core capping film.