CPU Core Die Power Management Through Thread Consolidation

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Solution Overview

Problem

Allocating different core dies of a CPU to different virtual machines results in sparse utilization of processor cores, leading to excess power usage and limited performance due to the need to power inactive components.

Innovation Solution

A hypervisor or firmware assigns VMs or threads to a first core die and disconnects power from a second core die with no active threads, while maintaining power to the first die, and migrates active threads to the first die, increasing the clock frequency of remaining active cores to maximize performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If different core dies are allocated to different virtual machines, then resource allocation flexibility is improved, but power consumption increases due to sparse utilization

Engineering Contradiction:
Improveresource allocation flexibilityVSAvoidpower consumption
Core Design Contradiction:
Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The patent consolidates multiple core dies into a single active core die by migrating all active threads from multiple core dies to one designated core die. This merging approach allows the system to maintain resource allocation flexibility while significantly reducing power consumption by powering down inactive core dies, thereby resolving the contradiction between adaptability and energy usage.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent implements dynamic core die selection where the hypervisor dynamically determines which core die should be active based on current workload requirements. The system can switch between different core dies or activate additional core dies when needed, providing adaptability while minimizing power consumption by keeping only the necessary core dies active at any given time.

Inventive Principle:
Principle #15Dynamics

2Reliability

If all core dies are powered on to handle sparse allocation, then system reliability is maintained, but power consumption increases

Engineering Contradiction:
Improvesystem reliabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent performs preliminary thread migration before powering down inactive core dies. By proactively migrating all active threads to a selected core die before shutdown, the system ensures that no active threads are left on powered-down core dies, thereby maintaining system reliability while enabling power savings through selective core die shutdown.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback mechanisms where the hypervisor continuously monitors thread distribution and core die utilization. Based on this feedback, the system dynamically adjusts which core dies remain active and which can be powered down, ensuring system reliability is maintained while optimizing power consumption through data-driven decisions.

Inventive Principle:
Principle #23Feedback

3Productivity

If inactive core dies remain powered on, then performance is maintained, but power savings are lost

Engineering Contradiction:
ImproveperformanceVSAvoidpower savings
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent extracts inactive core dies from the powered-on state by selectively powering down core dies that have no active threads. This extraction approach removes the energy consumption of inactive components while preserving system performance by ensuring all active threads are consolidated on remaining active core dies, thereby achieving both performance maintenance and power savings.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS20250306668A1Die power management
Publication Date: 2025.10.02 ADVANCED MICRO DEVICES INC
  • US20250306668A1 patent drawing
  • US20250306668A1 patent drawing
  • US20250306668A1 patent drawing

AI summary

A processor includes two or more core dies each including one or more processor cores and/or associated with one or more input/output dies. A hypervisor, firmware in a central processing unit (CPU), or software or firmware located outside of the CPU assigns virtual machines or threads to a first core die and disconnects power from a second core die with no active threads or cores, e.g., by adjusting one or more voltage regulators associated with the second core die, while still providing power to the first core die. In some implementations, active threads or processing cores are migrated from sparsely allocated processing cores or core dies into a reduced number of core dies. Power usage is minimized by disconnecting one or more inactive core dies from power while performance is maximized by increasing the clock frequency of remaining active core dies or remaining active processing cores located therein.