Processing Core Fault Testing via Low Power State Isolation
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Solution Overview
Problem
Conventional fault testing methods for processing cores are inadequate as they either rely on costly external testing, do not account for internal logic, or are destructive and limited to power-on or power-off states, failing to detect latent faults effectively during system operation.
Innovation Solution
The method involves leveraging low power or sleep states to perform fault testing, including structural testing, by isolating components, applying test vectors, and restoring state information to ensure continuous system operation and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If structural testing is performed during power-on or power-off states, then fault detection capability is improved, but system operation is disrupted and state integrity is compromised
Solution Approach 1:
The patent applies dynamics by transitioning the processing core between operational states and low-power states to enable testing. The system dynamically switches the processing core from an active state where it processes data to a low-power state where it can be tested without disrupting overall system operation, thus resolving the contradiction between fault detection capability and system operation continuity
Solution Approach 2:
The patent introduces a low-power state as an intermediary condition between full operation and complete shutdown. This intermediary state allows the processing core to be isolated for testing while preserving its operational context, enabling fault detection without permanently disrupting system operation or compromising state integrity
2Ease of manufacture
If functional testing is used to validate processing cores, then testing cost is reduced, but fault coverage is insufficient due to not accounting for internal logic
Solution Approach 1:
The patent applies local quality by tailoring the test vectors to specifically target the internal logic and architectural characteristics of the processing core. Instead of using generic functional tests, the system generates test vectors that are locally optimized to exercise specific internal logic paths, thereby achieving high fault coverage while maintaining cost-effectiveness
Solution Approach 2:
The patent implements self-service by enabling the processing core to perform self-testing during its low-power states. The core uses its own internal resources and logic to execute test vectors and detect faults within itself, eliminating the need for expensive external test equipment while achieving comprehensive fault coverage through self-diagnosis
3Reliability
If testing is performed during runtime operation, then fault detection at runtime is enabled, but state integrity of the component is compromised
Solution Approach 1:
The patent applies dynamics by creating a dynamic testing window where the processing core transitions to a low-power state specifically for testing purposes. This temporal separation allows testing to occur without permanently altering the component's operational state, thus enabling runtime fault detection while preserving state integrity when the core returns to its operational state
Solution Approach 2:
The patent segments the operational timeline into distinct phases: normal operation phase and testing phase. During the testing phase, the processing core is isolated in a low-power state, and during the normal operation phase, it functions normally. This segmentation allows testing to occur at runtime without compromising state integrity, as the testing activity is confined to dedicated time windows separated from operational activities
Data Source
AI summary
In various examples, one or more components or regions of a processing unit-such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.