Low-Resistivity Core Interconnect Wires for RC Delay Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As integrated circuit features are scaled down, interconnect delay due to resistive-capacitance effects and electromigration become significant issues, with refractory metals increasing resistivity and resistance, while diffusion barriers affect wire properties and reliability.
Innovation Solution
The formation of interconnect wires with a core of lower resistivity material surrounded by a jacket, where the core has a lower melting temperature and lower resistivity than the jacket, providing a diffusion barrier and anti-scattering properties, and the use of a diffusion barrier between the wire and the interlayer dielectric to reduce electromigration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refractory metals are used to reduce electromigration, then reliability is improved, but resistivity increases and RC delay worsens
Solution Approach 1:
The patent uses composite interconnect structures combining copper (low resistivity) with refractory metal liners (high electromigration resistance). The copper core provides low RC delay while the refractory metal coating prevents electromigration, resolving the contradiction between reliability and energy loss.
Solution Approach 2:
A diffusion barrier layer is introduced as an intermediary between the copper interconnect and the surrounding dielectric. This barrier prevents copper diffusion while maintaining electrical performance, allowing the use of low-resistivity copper without sacrificing reliability.
2Productivity
If feature size is scaled down to increase density, then productivity is improved, but RC delay and electromigration worsen
Solution Approach 1:
The patent changes material parameters (resistivity, melting point) rather than geometric parameters to address scaling issues. By using materials with fundamentally different properties (low-resistivity copper, high-melting-point refractory metals), the system maintains performance at smaller dimensions without being constrained by size reduction.
3Speed
If wire geometry is optimized to reduce RC delay, then speed is improved, but manufacturing complexity increases
Solution Approach 1:
Instead of optimizing the entire wire geometry, the patent applies local material quality improvements through multi-layer construction. Each layer (diffusion barrier, refractory metal liner, copper core) has specific local properties that collectively reduce RC delay without requiring complex overall wire geometry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces interconnect delay and electromigration, improving the reliability and performance of integrated circuits by minimizing resistive-capacitive delays and enhancing current density, while maintaining low resistance and resistance to thermal and mechanical stresses.
Implementation Method 1
the core material exhibits a lower resistivity than the jacket material, wherein the jacket material provides a diffusion barrier and anti-scattering properties
Implementation Method 2
the jacket material provides a diffusion barrier and anti-scattering properties
Implementation Method 3
the core material exhibits a lower melting temperature than the jacket material
Data Source
AI summary
A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1.