Multi-Core Host System Core-Local Timer Segmentation
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Solution Overview
Problem
Existing multi-core systems face performance and latency issues due to cross-core notifications and the need for central timer management, which leads to suboptimal real-time solution distribution across multiple cores.
Innovation Solution
Implementing core-local timers and interrupt locks to reduce cross-core notifications by enabling core-local signaling paths and process-specific management of data structures, allowing each core to manage its own real-time processes and timers, thereby minimizing latency and enhancing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a real-time extension is distributed over several cores in a multi-core system, then the theoretical computing power increases, but the performance deteriorates due to cross-core notifications, spinlocks, and access contention
Solution Approach 1:
The patent segments the real-time extension into core-local instances, with each core having its own real-time process and timer management. This segmentation eliminates cross-core notifications and spinlocks for timer operations, as each core independently manages its own real-time processes. The segmentation of data structures into core-local and global portions further reduces contention, allowing parallel execution without performance degradation.
Solution Approach 2:
The patent implements local quality by providing core-local timer management and core-local real-time processes for each processor core. Each core has dedicated resources (timers, process queues) that eliminate the need for cross-core access and synchronization. This local ownership principle ensures that time-critical operations remain on the same core, avoiding the performance penalties of inter-core communication and lock contention.
2Adaptability or versatility
If cross-core notifications are used for real-time process management, then process coordination is enabled, but latency increases due to inter-processor interrupts and signaling overhead
Solution Approach 1:
The patent extracts the timer management functionality from a centralized location and places it locally on each core. By taking out the timer operations from global/shared access and embedding them in core-local real-time processes, the system eliminates cross-core interrupts and signaling overhead for timer events. This extraction principle directly reduces latency by keeping time-critical operations on the same core where they are needed.
3Reliability
If spinlocks are used for protecting shared data structures, then data consistency is ensured, but system performance deteriorates due to atomic operations and cache locking overhead
Solution Approach 1:
The patent segments data structures into core-local portions (accessible without locks) and global portions (protected by spinlocks when necessary). By segmenting the data structures, the majority of access operations can proceed without spinlock overhead, as each core accesses its own local data structures. This segmentation dramatically reduces the frequency and duration of spinlock acquisitions, improving overall system performance while maintaining data consistency for shared resources.
4Quantity of substance
If local L2 caches are implemented per core, then memory bandwidth is increased, but access contention and serialization increase quadratically with the number of cores
Solution Approach 1:
The patent applies local quality by assigning core-local data structures and processes to each processor core, ensuring that the majority of data access operations occur within the local L2 cache of each core. This local access pattern maximizes the benefit of L2 caches by keeping frequently accessed data local, while minimizing cross-core cache coherence traffic and access contention. The local ownership model ensures that each core operates independently with its own data, reducing serialization effects.
Data Source
AI summary
An example of an embodiment of the invention relates to a host system comprising a plurality of cores, said host system being designed such that one real-time process and one core-local timer is run on each of the plurality of cores.