Core Logic Device Interrupt Control via Virtual Wire Unit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The removal of the INTR pin connection between the CPU and PIC in modern computer systems complicates interrupt control, leading to system crashes when certain operating systems, like Netware V5.1 & V6.0, automatically clear the redirection table contents, including preset settings, preventing proper interrupt signal assertion notification to the CPU.
Innovation Solution
A core logic device integrates a PIC, I/O APIC, virtual wire unit, and multiplexer to manage interrupt signals, using a virtual wire mode that outputs a control packet with a '111' code to ignore interrupt vectors before OS loading, and a redirection table for direct interrupt vector access after OS loading, ensuring uninterrupted interrupt service even without the INTR pin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the INTR pin connection between CPU and PIC is removed to simplify the system structure, then the device complexity is reduced, but the interrupt control reliability deteriorates and system crashes occur when operating systems clear the redirection table contents
Solution Approach 1:
The patent introduces a virtual wire unit as an intermediary component between the PIC and CPU. This virtual wire unit receives interrupt signals from the PIC and generates interrupt control packets that contain interrupt vector information, enabling the CPU to obtain interrupt vectors without requiring a direct INTR pin connection. The virtual wire unit acts as a mediator that maintains interrupt control functionality while allowing the physical pin connection to be removed.
Solution Approach 2:
The patent segments the interrupt control function into multiple independent components: the PIC handles interrupt signal reception and initial processing, the virtual wire unit generates interrupt control packets, and the CPU processes these packets. This segmentation allows each component to perform its specific function independently, maintaining system reliability while reducing overall complexity by eliminating the need for direct pin connections between components.
2Ease of operation
If the virtual wire unit outputs interrupt control packets with interrupt vectors before OS loading, then the interrupt control is simplified for the CPU, but the interrupt vector information may be incorrectly cleared when the OS initializes the redirection table
Solution Approach 1:
The patent implements preliminary action by having the virtual wire unit output interrupt control packets containing interrupt vector information before the operating system loads and initializes the redirection table. This allows the CPU to access interrupt vectors during the boot process and early system operation. The virtual wire unit is designed to preserve these previously outputted interrupt control packets even after the OS initialization, preventing their incorrect clearance and ensuring continuous availability of interrupt vector information.
Solution Approach 2:
The patent applies beforehand cushioning by creating a protective mechanism where the virtual wire unit maintains a copy of interrupt control packets that were outputted before OS loading. This cushioning effect ensures that even if the OS initialization process clears the redirection table contents, the interrupt vector information remains available through the virtual wire unit's preserved packets, preventing system failures.
3Productivity
If the PIC mode is used where the CPU reads interrupt vectors from the PIC after INTR pin assertion, then the interrupt control is straightforward, but the additional reading procedure complicates the interrupt control process and increases response time
Solution Approach 1:
The patent merges the interrupt vector information directly into the interrupt control packets generated by the virtual wire unit. Instead of requiring the CPU to separately read interrupt vectors from the PIC after detecting an interrupt signal, the virtual wire unit combines both the interrupt signal notification and the interrupt vector information into a single integrated packet structure. This merging eliminates the additional reading procedure and reduces interrupt control complexity while improving response speed.
Data Source
AI summary
A core logic device of a computer system includes a programmable interrupt controller (PIC), an input/output advanced programmable interrupt controller (I/O APIC) and a virtual wire unit. The PIC outputs a control signal to the virtual wire unit via an interrupt pin in response to an external interrupt signal asserted by a peripheral device before an operating system is loaded in the computer system. The virtual wire unit outputs an interrupt control packet to the CPU in response to the control signal wherein the interrupt vector contents carried by the interrupt control packet are ignored by the CPU. After the operating system is loaded in the computer system, the I/O APIC outputs another interrupt control packet to the CPU in response to the external interrupt signal.