System Core Logic Power Management Bypassing CPU Hardware Limits
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Solution Overview
Problem
Some lower cost or lower performance CPUs, suited for mobile applications, lack hardware support for deeper power saving modes, preventing system-level power savings by not allowing core logic to utilize built-in hardware for power reduction.
Innovation Solution
A method and system that enable system core logic to enter deeper power saving modes independently of normal power saving bus semantics by coordinating CPU and system core logic to implement power saving states beyond those supported by the CPU, using a bypass mechanism that accounts for latency requirements and supports multiple power saving levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the CPU lacks hardware support for deeper power saving modes, then device cost is reduced, but system power saving capability is limited
Solution Approach 1:
The patent introduces a power management mechanism that acts as an intermediary between the CPU and system core logic. This mechanism enables the system core logic to independently control power states of system components even when the CPU lacks hardware support for deep power saving modes. The power management logic monitors CPU activity and coordinates with system core logic to enter appropriate power states, effectively bridging the gap between limited CPU capabilities and system-level power management needs.
2Use of energy by moving object
If the system enters deeper power saving modes, then power consumption is reduced, but latency increases
Solution Approach 1:
The patent implements dynamic power state management where the system core logic can flexibly transition between different power states based on real-time system conditions. The mechanism dynamically adjusts power states of system components independently of CPU power states, allowing the system to enter deeper power saving modes when appropriate while maintaining the ability to quickly respond to interrupts or events. This dynamic approach optimizes the balance between power consumption and latency by selecting the most appropriate power state for each situation.
3Adaptability or versatility
If the CPU uses standard power saving bus semantics, then compatibility is maintained, but deeper power saving modes are not achieved
Solution Approach 1:
The patent segments the power management functionality into two independent parts: CPU power state management and system core logic power state management. This segmentation allows each component to operate independently at its appropriate power state level. The CPU can maintain standard power saving semantics for compatibility, while the system core logic simultaneously manages deeper power states for system components. This separation of concerns enables both compatibility and deeper power saving capabilities to coexist without conflict.
Data Source
AI summary
A system including power savings modes, the system including a processor that supports bus semantics in its hardware for a power state of a first level, wherein the first level is lowest power level the processor is able to enter, a system core logic module coupled to the processor, and a memory, coupled to the system core logic module, storing instructions, which when executed by the system, causes the system core logic to be notified of an impending processor idle state that is compatible with the latency required for system core logic power savings modes and wherein, in response to being notified of an impending processor idle state, the system core logic implements thread, core, or package level power saving idle modes lower than supported by the first level based on a latency hierarchy and independent of normal power saving bus semantics.