Core Matrix Bypass Control for Defect-Tolerant Chip Yield
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Solution Overview
Problem
Existing systems face significant waste and resource inefficiencies due to discarding entire chips or boards when defects occur in specific cores during manufacturing or usage, leading to lower yields and shorter lifetimes, especially in high-performance computing applications like hashing, encryption, and artificial intelligence.
Innovation Solution
A method and device that monitor core operations, bypass defective cores by modifying their clock signals, and utilize remaining functional cores to maintain system performance, extending the lifetime and yield of chips, boards, and racks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a defect is identified in a specific core through chip testing, then the chip is discarded to ensure reliability, but this decreases chip yield and wastes resources
Solution Approach 1:
The chip is segmented into multiple independent cores that can operate separately. When a defect is detected in one core, only that specific core is isolated while the other cores continue to function, allowing the chip to maintain partial functionality without being completely discarded.
Solution Approach 2:
Different parts of the chip (different cores) have different operational statuses. Functional cores continue to operate with normal quality standards, while defective cores are marked and isolated. This local differentiation allows the chip to maintain overall functionality despite localized defects.
2Productivity
If a chip with a defective core is used, then chip yield is improved, but system reliability deteriorates due to the defective core
Solution Approach 1:
The defective core is extracted or isolated from the functional cores through bypass circuitry. This allows the defective core to be removed from the computational path while preserving the functionality of the remaining cores, thus maintaining system reliability despite using a chip with a defective core.
Solution Approach 2:
Bypass circuitry is introduced as an intermediary component between the defective core and the rest of the system. This intermediary structure redirects computational tasks away from the defective core to functional cores, ensuring that system operations maintain reliability without requiring the defective core.
3Reliability
If entire chips are replaced due to core defects, then system reliability is maintained, but time and resources are wasted
Solution Approach 1:
Bypass circuitry is pre-configured during chip manufacturing to enable future isolation of defective cores. When a core defect occurs during operation, the bypass paths are already in place and can be activated immediately, eliminating the need for time-consuming chip replacement and enabling rapid fault tolerance.
4Speed
If finer circuitry line widths are used, then computational performance is improved, but manufacturing yield decreases
Solution Approach 1:
Bypass circuitry is built into the chip architecture during manufacturing to provide a cushion against potential core defects. This pre-prepared fault tolerance mechanism compensates for the lower yield associated with finer circuitry line widths by ensuring that even if defects occur, the chip can continue to function with reduced performance rather than complete failure.
Data Source
AI summary
The present disclosure relates to a method and device for performing performance harvesting, where multiple cores are embedded in a matrix structure and configured to perform their operations independently, for allowing the remaining cores, which operate normally despite some cores not functioning, to independently produce results of operations by harvesting their respective performances, by being configured to test the operations of each of the multiple cores, bypass cores with defects (or faults, fails, etc.), and exclude the defected cores from the operations.