Per-Thread Core Memory Bandwidth Control for QoS Contention
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Solution Overview
Problem
Processor cores in multicore processors face unpredictable and degraded quality of service due to contention for shared resources like caches and memory bandwidth, which existing technologies struggle to manage efficiently.
Innovation Solution
Implementing dynamic hardware controllers within cores to manage memory bandwidth allocation and cache bandwidth allocation using MSRs such as IA32_PQR_ASSOC and IA32_QoS_Core_BW_Thrtl_N, enabling fine-grained control and monitoring of memory bandwidth to ensure fair allocation and reduce contention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dynamic hardware controllers are implemented within cores to manage memory bandwidth allocation, then quality of service and response speed improve, but device complexity increases
Solution Approach 1:
The patent introduces memory bandwidth monitors and hardware controllers as intermediary components between application threads and shared memory resources. These intermediaries actively manage bandwidth allocation by monitoring usage patterns and dynamically adjusting access rates, thereby improving quality of service without requiring fundamental changes to the core processor architecture.
Solution Approach 2:
The patent segments memory bandwidth management into per-thread or per-application allocations using control registers (such as IA32_PQR_ASSOC and IA32_QoS_Core_BW_Thrtl_N). Each segment can be independently monitored and controlled, allowing fine-grained bandwidth management while keeping the overall system structure manageable through modular registration and control mechanisms.
2Productivity
If fine-grained control of memory bandwidth is implemented, then throughput and application performance increase, but ease of operation decreases
Solution Approach 1:
The patent implements self-service mechanisms where the hardware automatically monitors memory bandwidth usage and adjusts allocations based on pre-configured thresholds and policies stored in control registers. The system serves itself by detecting bandwidth contention and dynamically adjusting access rates without requiring manual intervention, thereby maintaining high throughput while simplifying operation through automated management.
Solution Approach 2:
The patent incorporates feedback loops where memory bandwidth monitors continuously track actual usage against allocated quotas and adjust bandwidth allocation in real-time. This feedback mechanism enables the system to automatically respond to changing workload conditions, maintaining optimal throughput while reducing the operational burden on users through adaptive, self-regulating behavior.
3Speed
If hardware controllers monitor and control memory bandwidth in real-time, then response speed to changing conditions improves, but use of energy increases
Solution Approach 1:
The patent implements periodic monitoring and control actions rather than continuous operation. The hardware controllers sample memory bandwidth usage at defined intervals and adjust allocations based on these periodic measurements, enabling responsive management of bandwidth changes while reducing energy consumption by keeping controllers in low-power states between monitoring cycles.
Data Source
AI summary
Techniques for controlling bandwidth in a core are described. An exemplary core includes a memory bandwidth monitor per thread local to the core, each thread's local bandwidth monitor to at least allocate bandwidth for memory requests originating from the thread according to a class of service level stored in a field of quality of service (QOS) model-specific register (MSR), the class of service level pointed to by a class of service field in a platform quality of service MSR; and execution resources to support execution of at least one thread of the core.