Core Memory Bandwidth Control for Thread-Level QoS
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Solution Overview
Problem
Processor cores in multicore processors face unpredictable and degraded quality of service due to contention for shared resources such as caches and memory bandwidth, which existing technologies like Resource Director Technology struggle to address effectively.
Innovation Solution
Implementing dynamic hardware controllers within cores to manage memory bandwidth allocation and cache bandwidth allocation, using MSRs to map threads to classes of service and adjust throttling levels, enabling fine-grained control and monitoring to optimize resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dynamic hardware controllers are implemented within cores to manage memory bandwidth allocation, then quality of service and throughput are improved, but device complexity increases
Solution Approach 1:
The patent introduces memory bandwidth monitors and hardware controllers as intermediary components within the core architecture. These intermediaries sit between the execution units and the memory subsystem, dynamically regulating bandwidth allocation to different threads based on priority levels and configured limits, thereby improving quality of service without requiring complete redesign of the memory hierarchy
Solution Approach 2:
The patent segments memory bandwidth control into thread-specific priority levels and configurable limit settings. Each thread can be assigned different priority levels (e.g., high, medium, low) and bandwidth limits, allowing fine-grained control over resource allocation. This segmentation enables independent management of bandwidth for different applications or workloads running on the same core
2Productivity
If fine-grained control and monitoring are implemented to optimize resource usage, then quality of service is improved, but ease of operation deteriorates
Solution Approach 1:
The hardware controllers automatically monitor memory bandwidth usage and enforce configured limits without requiring manual intervention. The system self-regulates by tracking actual bandwidth consumption against allocated limits and dynamically adjusting access permissions, thereby maintaining high quality of service while reducing operational complexity through automation
Solution Approach 2:
The patent implements feedback mechanisms where memory bandwidth monitors continuously track actual bandwidth consumption and provide this information back to the hardware controllers. This feedback loop enables dynamic adjustment of bandwidth allocation based on real-time conditions, allowing the system to optimize resource usage automatically while maintaining simple configuration through initial limit settings
Data Source
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AI summary
Techniques for controlling bandwidth in a core are described. An exemplary core includes a memory bandwidth monitor per thread local to the core, each thread's local bandwidth monitor to at least allocate bandwidth for memory requests originating from the thread according to a class of service level stored in a field of quality of service (QoS) model-specific register (MSR), the class of service level pointed to by a class of service field in a platform quality of service MSR; and execution resources to support execution of at least one thread of the core.