Core Power Supply ESD Protection in Semiconductor ICs
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Solution Overview
Problem
Semiconductor integrated circuit devices face increased chip size due to the arrangement of external connection pads, and existing configurations lack electrostatic discharge (ESD) protection for the core power supply, making it vulnerable.
Innovation Solution
A configuration with multiple rows of external connection pads, where a first pad row is partially located in the core region and connected to the core power supply, and a second pad row is outwardly located, connected to I/O cells, including ESD protection circuits for enhanced ESD protection without increasing the chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If pads are arranged in multiple rows with the core power supply pads forming an innermost row, then the chip size increase is reduced, but the core power supply becomes vulnerable to ESD due to lack of I/O cells for protection
Solution Approach 1:
The patent introduces a new spatial dimension by placing ESD protection circuits in the I/O region rather than within the core region. The core power supply pads in the innermost row are electrically connected to ESD protection circuits located in the outer I/O region through power supply interconnects, effectively extending the protection capability from the core to the I/O region without increasing core area.
Solution Approach 2:
The patent introduces power supply interconnects as intermediary elements that electrically connect the core power supply pads to the ESD protection circuits. These interconnects act as mediators, allowing the ESD protection functionality to be provided indirectly to the core power supply through the I/O region without direct placement of protection circuits in the core region.
2Area of stationary object
If external connection pads are arranged in a single row along the periphery, then the device area increases, but the ESD protection structure becomes simpler
Solution Approach 1:
The patent segments the pad arrangement into multiple rows: an innermost row for core power supply pads, intermediate rows for other functions, and an outermost row for I/O pads. This segmentation allows different functional zones to be clearly defined and optimized independently, with the core power supply pads protected by ESD circuits in the I/O region.
3Power
If core power supply pads are placed in the core region, then power supply to the core is sufficient, but the pads lack ESD protection circuits
Solution Approach 1:
The patent merges the core power supply function with ESD protection functionality by electrically connecting the core power supply pads to ESD protection circuits through power supply interconnects. This merging allows a single pad structure to serve dual purposes: power supply to the core and ESD protection, eliminating the need for separate unprotected power pads.
Data Source
AI summary
Disclosed herein is a configuration for ensuring ESD protection capability for a core power supply of a semiconductor integrated circuit device, without causing an increase in the circuit area. A first pad row in a core region includes a first pad for core power supply. The first pad is connected to a core power supply interconnect, and supplied with a power supply potential or a ground potential. A second pad row provided outwardly from the first pad row includes a second pad for core power supply. The second pad is supplied with the same power supply or ground potential as the first pad for core power supply, and connected to an I/O cell for core power supply.