Synchronous and Quasi-Synchronous Core Program Migration
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Solution Overview
Problem
Loosely coupled fault tolerant computers face challenges in increasing processing performance without requiring additional hardware or changing the existing hardware configuration, as increasing the number of synchronous cores necessitates enhanced communication bandwidth and hardware resources.
Innovation Solution
A computer system with synchronous and quasi-synchronous core processing units that switch programs and execute them in parallel, with the quasi-synchronous units migrating tasks between each other and the synchronous units, allowing for parallel execution without additional communication bandwidth or hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of synchronous cores is increased to improve processing performance, then processing performance is improved, but communication bandwidth and hardware resources are insufficient
Solution Approach 1:
The patent divides cores into two categories: synchronous cores that maintain strict synchronization for critical tasks, and asynchronous cores that operate independently for less time-sensitive tasks. This segmentation allows the system to scale processing capacity without proportionally increasing synchronization communication bandwidth requirements, as asynchronous cores do not require the same level of inter-core communication.
Solution Approach 2:
The patent introduces dynamic task migration capability that allows tasks to be moved between synchronous and asynchronous cores based on real-time system conditions and task characteristics. This dynamic allocation optimizes resource utilization and allows the system to handle varying workloads efficiently without requiring fixed hardware configurations for each core type.
2Productivity
If the number of synchronous cores is increased to improve processing performance, then processing performance is improved, but hardware configuration must be changed
Solution Approach 1:
The patent creates a universal core architecture where both synchronous and asynchronous cores can execute the same instruction sets and access the same memory resources. This multi-functionality allows existing hardware to serve dual purposes, eliminating the need for specialized hardware configurations when scaling the system.
Solution Approach 2:
The patent implements virtualization techniques that allow multiple logical cores to share physical hardware resources. By creating virtual copies of core functions and using time-multiplexing on shared hardware, the system can provide the functionality of multiple synchronous cores without proportionally increasing physical hardware complexity.
3Productivity
If additional communication bandwidth is provided to support more synchronous cores, then processing performance is improved, but system complexity increases
Solution Approach 1:
The patent introduces a message passing interface and intermediary software layer that manages communication between cores. This intermediary abstracts the complexity of direct peer-to-peer communication, allowing cores to interact through standardized protocols and reducing the need for complex point-to-point communication hardware for each core pair.
Data Source
AI summary
A synchronous core processing unit executes the same program as a program executed by another computer for an execution unit at a synchronization timing synchronized with a synchronous core processing unit of the other computer, and migrates the program being executed for which migration is requested according to characteristics of the program to a quasi-synchronous core processing unit. The quasi-synchronous core processing unit executes the program migrated from the synchronous core processing unit, and then migrates the program to the synchronous core processing unit. The synchronous core processing unit outputs, to an output comparison machine, an execution result obtained by executing the program migrated from the quasi-synchronous core processing unit at the synchronization timing.