Core Processor Rate Limiter for Multi-Core Memory Access Control
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Solution Overview
Problem
Multi-core processors in avionics systems face inefficiencies due to core interference, leading to disabled cores and inefficient hardware utilization, especially when implementing ARINC 653 systems, which were designed for single-core processors.
Innovation Solution
A multi-core processor system with core processor rate limiters using a token bucket process to constrain memory access rates, ensuring each core operates within an expected value, thereby isolating cores and preventing interference, and including a master controller system for coordinated memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple cores share common memory resources in a multi-core processor system, then hardware utilization efficiency is improved, but core interference occurs leading to performance degradation and violation of partition guarantees
Solution Approach 1:
The patent applies segmentation by dividing the memory access control into core-specific rate limiters, where each core has its own access rate constraint. This segments the shared memory resource into controlled access channels per core, preventing one core from monopolizing memory bandwidth while allowing multiple cores to operate simultaneously, thus resolving the contradiction between hardware utilization and partition guarantees.
Solution Approach 2:
The patent changes the parameter of memory access rate by introducing rate limiting mechanisms that dynamically control the number of memory accesses per core within a time window. By adjusting access rate parameters individually for each core, the system enables multiple cores to share memory resources efficiently while preventing interference that would violate partition guarantees.
2Reliability
If memory access rate is constrained for each core, then DDR bandwidth is guaranteed and processing capacity is enhanced, but access flexibility is reduced
Solution Approach 1:
The patent implements dynamic rate limiting where the memory access rate constraints are adjusted based on real-time system conditions and core behavior patterns. The rate limiter adapts the access rate parameters dynamically, allowing cores to access memory more freely when needed while enforcing constraints when bandwidth guarantee is critical, thus resolving the contradiction between bandwidth guarantee and access flexibility.
3Speed
If cores operate asynchronously without rate limiting, then processing speed is improved, but excessive memory access degrades processor capacity for other cores
Solution Approach 1:
The patent applies preliminary anti-action by implementing rate limiters that proactively prevent excessive memory access before it can occur. The rate limiter monitors and constrains each core's memory access rate in advance, preventing any single core from degrading the processor capacity available to other cores, thus maintaining overall system productivity while allowing asynchronous operation.
Data Source
AI summary
A multi-core processor system includes a number of cores, a memory system, and a common access bus. Each core includes a core processor; a dedicated core cache operatively connected to the core processor; and, a core processor rate limiter operatively connected to the dedicated core cache. The memory system includes physical memory; a memory controller connected to the physical memory; and, a dedicated memory cache connected to the memory controller. The common access bus interconnects the cores and the memory system. The core processor rate limiters are configured to constrain the rate at which data is accessed by each respective core processor from the memory system so that each core processor memory access is capable of being limited to an expected value.