Core Selection Logic for ML Training Power Reduction

The patent divides the training process into multiple phases and segments cores into different activation states. During early training phases, fewer cores are activated while learning rates are higher. As training progresses and learning rates decrease, additional cores are activated. This segmentation allows the system to achieve complete training reliability while reducing overall power consumption by not all cores operating at full capacity simultaneously.

The patent implements dynamic core activation where the number of active cores changes over time based on training progress. The system dynamically adjusts which cores are active based on epoch-based scheduling and learning rate decay patterns. This dynamic approach ensures training completeness is achieved through progressive core activation while minimizing peak power consumption and overall energy usage.

The patent applies local quality by tailoring training parameters and core activation patterns to specific hardware characteristics. Different cores or core groups are activated based on their specific properties (e.g., compute capability, memory bandwidth). Training operations are optimized for the specific hardware architecture being used, such as adjusting precision formats or data types based on hardware capabilities. This local optimization improves training efficiency without requiring complex universal training processes.

The patent utilizes parameter changes to adapt the training process to hardware characteristics. Learning rates, precision formats, and core activation patterns are adjusted as parameters based on hardware properties. The system changes training parameters dynamically to match hardware capabilities, such as switching between different data precisions or adjusting batch sizes based on memory bandwidth constraints. This parameter adaptation improves efficiency while maintaining manageable process complexity through automated parameter tuning.