Core-Shell Nanostructured Channels for Higher-Mobility GAA FETs
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Solution Overview
Problem
Current semiconductor technologies face challenges in enhancing charge carrier mobility in FET devices, which limits their switching speeds and drive currents due to the complexity of scaling down semiconductor dimensions.
Innovation Solution
The implementation of core-shell nanostructures, where nanostructured core regions are wrapped by epitaxially grown nanostructured shell regions, induces strain and tunes the energy bandgap and crystal orientation in channel regions, improving charge carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor device dimensions are scaled down to increase storage capacity and processing speed, then device density and processing capability are improved, but manufacturing process complexity increases
Solution Approach 1:
The patent implements core-shell nanostructures where a core semiconductor material is surrounded by a shell semiconductor material with different properties. This nested configuration allows multiple functional layers to be integrated at the nanoscale, enabling complex device functionality within a compact structure that simplifies the overall manufacturing process despite the advanced device dimensions
Solution Approach 2:
The patent employs composite semiconductor structures combining different semiconductor materials (e.g., Si/SiGe, Ge/Si) with distinct properties in a core-shell configuration. This composite approach enables simultaneous optimization of carrier mobility, strain engineering, and bandgap control, achieving high performance without proportionally increasing manufacturing complexity
2Ease of manufacture
If conventional semiconductor structures are used in scaled devices, then manufacturing simplicity is maintained, but charge carrier mobility deteriorates
Solution Approach 1:
The patent modifies the crystal structure and material composition parameters by introducing strained semiconductor layers with different lattice constants. The strain engineering changes the physical parameters of the semiconductor material, enhancing carrier mobility from typical values to significantly improved values while maintaining compatibility with existing manufacturing processes
Solution Approach 2:
The patent applies different material properties locally within the device structure by positioning specific semiconductor materials (e.g., SiGe source/drain regions, Si channel) at specific locations. This local differentiation of material quality optimizes carrier mobility in the channel region while maintaining ease of manufacture through selective material placement rather than complete structure redesign
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases switching speeds and drive currents of FET devices by 20% to 50% compared to devices without core-shell nanostructures, enhancing overall performance.
Implementation Method 1
nanostructured core regions wrapped by epitaxially grown nanostructured shell regions, which induce strain and modify the energy bandgap and crystal orientation to improve charge carrier mobility
Data Source
AI summary
The structure of a semiconductor device with core-shell nanostructured channel regions between source/drain regions of FET devices and a method of fabricating the semiconductor device are disclosed. A semiconductor device includes a substrate, a stack of nanostructured layers with first and second nanostructured regions disposed on the substrate, and nanostructured shell regions wrapped around the second nanostructured regions. The nanostructured shell regions and the second nanostructured regions have semiconductor materials different from each other. The semiconductor device further includes first and second source/drain (S/D) regions disposed on the substrate and a gate-all-around (GAA) structure disposed between the first and second S/D regions. Each of the first and second S/D regions includes an epitaxial region wrapped around each of the first nanostructured regions and the GAA structure is wrapped around each of the nanostructured shell regions.