Core-Side Predictor for Parallel Memory Access Latency
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Solution Overview
Problem
The large multi-GB cache in CPU systems incurs network latency due to its hierarchical organization, which dilutes the overall value by increasing latency on the miss path, especially when the hit rate is poor, and existing solutions fail to effectively reduce this latency.
Innovation Solution
Implementing a core-side predictor that identifies likely cache misses and allows direct access to main memory in parallel with cache levels, reducing latency by predicting misses and bypassing cache latency through parallel requests to both cache and memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a large multi-GB cache is implemented in CPU systems, then the cache capacity is increased, but network latency is incurred due to hierarchical organization
Solution Approach 1:
The system performs preliminary action by predicting cache misses before they occur. The predictor identifies likely cache misses in advance, allowing the system to initiate parallel access to main memory before the cache miss is fully processed, thereby reducing the effective latency experienced by the CPU.
Solution Approach 2:
The patent introduces a new dimension of parallelism by implementing both cache access and main memory access simultaneously through parallel request paths. This dimensional change allows the system to bypass the sequential cache-then-memory access pattern, effectively reducing the time penalty for cache misses.
2Quantity of substance
If hierarchical cache organization is used, then cache capacity is increased, but latency on the miss path is increased
Solution Approach 1:
The predictor performs preliminary identification of likely cache misses, enabling the system to prepare parallel memory access requests in advance. This preliminary action reduces the effective miss path latency by overlapping the cache check with early memory access preparation.
Solution Approach 2:
The patent introduces an intermediary prediction mechanism that mediates between the cache and main memory. The predictor acts as an intermediary that identifies miss candidates and triggers parallel memory access, effectively bridging the latency gap between cache and memory without requiring sequential access.
3Loss of time
If parallel access to cache and main memory is implemented, then latency on miss path is reduced, but device complexity is increased
Solution Approach 1:
The predictor serves as a relatively simple intermediary component that enables complex parallel access functionality. By placing the prediction logic at the cache level rather than requiring complex coordination throughout the memory hierarchy, the patent reduces overall system complexity while achieving latency reduction.
Solution Approach 2:
The patent segments the memory access function into independent parallel paths: one for cache access and another for main memory access. This segmentation allows each path to operate independently, reducing the complexity of coordination while maintaining the performance benefits of parallel access.
Data Source
AI summary
Latency on the miss path to a cache level in a CPU module is reduced by predicting when a cache miss is likely. Main memory is directly accessed in parallel with the access to the cache level in the CPU module based on the prediction that a cache miss is likely in the cache level.