Core-Specific Encryption in Multi-Core Processors
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Solution Overview
Problem
Multi-core processors lack the capability to encrypt and decrypt data securely between cores and external devices, leading to inadequate cybersecurity, as they do not support core-specific encryption and decryption.
Innovation Solution
Implementing a system with a multi-core processor that includes core-specific memories and a shared memory, where each core can encrypt and decrypt data using a secret key, ensuring that encrypted data is accessible only to the intended core, and using low-latency encryption algorithms to minimize processing delay and memory consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional encryption techniques are used in multi-core processors, then data can be encrypted for external transmission, but cores cannot securely encrypt/decrypt data from each other's perspective
Solution Approach 1:
The patent divides the encryption system into core-specific segments by providing separate encryption keys and crypto-states for each core. Each core has its own unique encryption identity, allowing independent encryption and decryption operations. This segmentation enables Core A to encrypt data that only Core A can decrypt, while Core B has separate encryption capabilities, resolving the limitation of conventional multi-core processors that treat all cores as a single encryption entity.
Solution Approach 2:
The patent implements local quality by assigning unique encryption properties to each core. Each core possesses its own secret key and crypto-state stored in dedicated core memory, creating localized security zones. This allows each core to have customized encryption characteristics tailored to its specific security requirements, rather than using a uniform encryption approach across all cores.
2Adaptability or versatility
If encrypted data is stored in shared memory accessible to all cores, then data can be shared between cores, but security is compromised as other cores can access the encrypted data
Solution Approach 1:
The patent segments memory access rights by core identity. Each core has authorized access only to encrypted data that was specifically encrypted for it, while other cores are restricted from accessing that data even if physically present in shared memory. This is achieved through core-specific encryption keys and access control mechanisms that verify the requesting core's identity before allowing decryption.
Solution Approach 2:
The patent introduces an intermediary verification mechanism that checks whether a core is authorized to access specific encrypted data before allowing decryption. This intermediary layer sits between the shared memory and the core, validating the core's identity and permissions, thereby enabling secure data sharing only with authorized cores while blocking unauthorized access.
3Reliability
If encryption is implemented in multi-core processors, then data security between cores is improved, but processing latency and memory consumption increase
Solution Approach 1:
The patent performs preliminary action by pre-generating and storing core-specific secret keys and crypto-states in each core's dedicated memory before data transmission occurs. This preparation work is done in advance, so when encryption/decryption is needed, the system can quickly retrieve pre-computed cryptographic materials rather than performing complex key generation and setup operations in real-time, thereby reducing processing latency.
Solution Approach 2:
The patent implements self-service by enabling each core to independently perform encryption and decryption operations using its own stored crypto-state without requiring external cryptographic assistance. Each core manages its own cryptographic materials and performs cryptographic operations autonomously, eliminating the need for centralized cryptographic processing that would introduce additional latency and memory overhead.
Data Source
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AI summary
Systems and methods for processor core unique encryption are described herein. In certain embodiments, a system includes a multi-core processor comprising a plurality of cores. The system also includes a shared memory accessible to the plurality of cores. Further, the system includes a plurality of core memories, wherein each core memory is exclusively accessible to an associated core in the plurality of cores. Moreover, one or more cores in the plurality of cores creates encrypted data accessible to the one or more cores such that the encrypted data is secured from being accessed by one or more other cores in the plurality of cores. Additionally, the one or more cores store a crypto-state within associated core memories in the plurality of core memories.