Core-Based Speculative Page Fault Lists to Reduce Consecutive Faults
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Solution Overview
Problem
Conventional processors face performance loss due to frequent consecutive page faults, as software typically identifies patterns conservatively and only considers the single page range that caused the fault, failing to optimize memory usage in workloads with frequent data accesses.
Innovation Solution
The processor provides additional hints to the software page fault handler, including a speculative page fault list with optional pages and sizes, allowing the operating system to optimize memory usage by faulting in data as needed, reducing the number of subsequent faults through speculative execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software conservatively identifies patterns and only considers the single page range that caused the fault, then reliability is improved, but productivity deteriorates due to frequent consecutive page faults
Solution Approach 1:
The patent applies preliminary action by having the processor generate a speculative page fault list that predicts future page faults before they occur. The circuitry looks ahead at upcoming instructions and pre-identifies pages that will likely be accessed, allowing the operating system to fault in these pages in advance, thereby reducing consecutive page faults and improving memory access efficiency while maintaining reliable pattern identification
Solution Approach 2:
The patent transitions from single-page fault handling to multi-page speculative fault prediction by adding a new dimension of lookahead analysis. The circuitry examines multiple upcoming instructions beyond the current faulting page, creating a speculative page fault list that spans multiple pages and instructions, thus moving from one-dimensional conservative single-page handling to multi-dimensional speculative multi-page prediction
2Productivity
If the processor provides speculative hints for multiple optional pages, then productivity is improved by reducing page faults, but device complexity increases
Solution Approach 1:
The patent applies partial action by generating speculative page fault lists with a limited scope - it speculates about a predetermined number of upcoming instructions rather than analyzing all possible future instructions. This partial lookahead provides sufficient hints to reduce consecutive page faults while limiting the computational complexity and circuitry requirements to manageable levels
Solution Approach 2:
The patent introduces an intermediary speculative page fault list that acts as a mediator between the processor's instruction stream and the operating system's page fault handler. This intermediary structure consolidates speculative information from multiple instructions into a organized list format, simplifying the interface and reducing complexity while enabling productive page fault reduction
Data Source
AI summary
An embodiment of an integrated circuit may comprise an instruction decoder to decode one or more instructions to be executed by a core, and circuitry coupled to the instruction decoder, the circuitry to determine if a decoded instruction involves a page to be fetched, and determine one or more hints for one or more optional pages that may be fetched along with the page for the decoded instruction. Other embodiments are disclosed and claimed.