Core Switch Cache Allocation for PCI-Express Storage Devices

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Solution Overview

Problem

Electronic devices with the PCI-Express protocol cannot effectively distribute cache space to storage devices based on their types, such as AHCI and NVME devices, leading to inefficient data exchange.

Innovation Solution

A system and method that includes identification, information acquisition, distribution, initialization, and detection modules to identify storage device types, acquire efficiency information, compute and allocate cache space using a formula, and manage cache distribution dynamically based on device types and efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If PCI-Express protocol is used for communication between electronic device and storage devices, then communication speed and data exchange efficiency are improved, but the electronic device fails to identify storage device types, leading to inability to distribute cache space effectively

Engineering Contradiction:
Improvedata exchange speedVSAvoidcache space distribution capability
Core Design Contradiction:
SpeedVSAdaptability or versatility

Solution Approach 1:

The patent introduces a core switch as an intermediary component between the electronic device and storage devices. The core switch includes a buffer cache that acts as a mediator to manage cache space distribution. This intermediary enables the system to achieve both high-speed data exchange through PCI-Express and effective cache space distribution by having the core switch identify storage device types and allocate cache resources accordingly.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the cache management function by separating the identification and distribution tasks. The core switch's buffer cache is divided into multiple cache partitions, each allocated to specific storage devices based on their types (AHCI or NVME). This segmentation allows differentiated cache management for different storage device types while maintaining high-speed communication through the PCI-Express protocol.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If fixed capacity buffer cache is allocated to core switch, then cache space is available for data exchange, but cache space cannot be dynamically distributed to different storage devices based on their types and efficiency

Engineering Contradiction:
Improvecache space availabilityVSAvoiddata exchange efficiency
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The patent implements dynamic cache space distribution by having the core switch identify storage device types (AHCI or NVME) and allocate buffer cache space accordingly. The system dynamically adjusts cache allocation based on device characteristics and real-time efficiency metrics, allowing the fixed physical buffer cache to be flexibly distributed to maximize data exchange productivity for different storage device types.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the allocation parameters of cache space based on storage device types and performance metrics. The core switch monitors data exchange efficiency and adjusts cache space distribution parameters dynamically, allocating more cache space to high-performance NVME devices when appropriate while maintaining adequate space for AHCI devices, thereby optimizing overall system productivity.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10042769B2System and method for managing cache space and electronic device employing same
Publication Date: 2018.08.07 NANNING FUGUI PRECISION IND CO LTD
  • US10042769B2 patent drawing
  • US10042769B2 patent drawing
  • US10042769B2 patent drawing

AI summary

A method for managing cache space between one electronic device and multiple storage devices includes identifying and quantifying storage devices connected to an electronic device, and acquiring efficiency information of each identified storage device on preset occasions. Cache space of each storage device is computed on being connected to or being disconnected from the electronic device, taking account of information acquired as to efficiency and quantity of each of the storage devices. A core switch of the electronic device is controlled to allocate a computed cache space to a storage device.