Core Tightly Coupled Lockstep Mechanism for ADAS Functional Safety

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current solutions for achieving high functional safety in autonomous driving systems, such as Advanced Driver Assistance Systems (ADAS), face challenges due to the limitations of traditional error reduction techniques and the high cost and performance impact of dual CPU implementations, which are not effectively addressing core failure rates and software compatibility issues.

Innovation Solution

The implementation of a core tightly coupled lockstep mechanism that provides fault coverage across computing processor cores without requiring CPU-level determinism, leveraging main-band and side-band interfaces to compare checksums of output bits from two cores, ensuring redundancy and functional safety while being transparent to software and minimizing physical and performance impacts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dual CPU implementations are used for redundancy, then functional safety is improved, but cost and performance overhead increase significantly

Engineering Contradiction:
Improvefunctional safetyVSAvoidperformance overhead
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent merges redundancy functionality into a single CPU socket by implementing lockstep dual-cores within one processor package. Instead of using two separate CPU sockets with full duplication of memory controllers and other components, the invention combines the redundant processing capability into one socket, reducing overall system cost and resource overhead while maintaining ASIL-D functional safety compliance.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If dual CPU implementations are used for redundancy, then fault coverage is improved, but software compatibility and portability become problematic

Engineering Contradiction:
Improvefault coverageVSAvoidsoftware compatibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent uses identical binary images on both lockstep cores, ensuring that the same software runs on both processors. This approach maintains software compatibility and portability because existing software can be deployed without modification. The redundancy is achieved at the hardware execution level rather than requiring software awareness or special dual-CPU configurations.

Inventive Principle:
Principle #26Copying

3Reliability

If socket-level determinism is implemented for functional safety, then comprehensive safety coverage is achieved, but cost and complexity increase

Engineering Contradiction:
Improvefunctional safety coverageVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies determinism locally at the core level rather than requiring global socket-level determinism. The lockstep dual-cores provide deterministic execution and fault coverage for critical functions, while other system components can operate with relaxed requirements. This localized approach achieves necessary functional safety coverage without the excessive complexity of full socket-level determinism.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10946866B2Core tightly coupled lockstep for high functional safety
Publication Date: 2021.03.16 INTEL CORP
  • US10946866B2 patent drawing
  • US10946866B2 patent drawing
  • US10946866B2 patent drawing

AI summary

Methods and apparatus relating to provision of core tightly coupled lockstep for high functional safety are described. In an embodiment, a master core, coupled to a slave core, executes one or more operations to support Advanced Driver Assistance Systems (ADA) or autonomous driving. The master core and the slave core receive the same input signal and core tightly couple logic causes generation of a signal in response to comparison of a first output from the master core and a second output from the slave core. The generated signal causes an interruption of the one or more operations in response to a mismatch between the first output and the second output. Other embodiments are also disclosed and claimed.