Core-to-core links bypass interconnects in SoC arrays
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Solution Overview
Problem
Current data transfer between cores in systems on a chip (SoCs) is inefficient due to the need for data to pass through core-to-core interfaces, resulting in latency and suboptimal memory usage.
Innovation Solution
Implementing direct core-to-core communication links within an array of data processing engines in SoCs, allowing cores to bypass interconnects and memory modules, enabling direct data transmission between neighboring cores without external buffers or memory elements, thereby reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If data passes through core-to-core interface, then data transfer between cores is enabled, but latency increases and memory efficiency decreases
Solution Approach 1:
The patent extracts the data transfer path from the traditional memory-based route and creates a direct core-to-core communication path. By removing the intermediate memory access step, the data transfer mechanism is simplified to achieve lower latency and higher efficiency without requiring complex memory management operations.
Solution Approach 2:
The patent introduces a dedicated core-to-core interface as an intermediary communication channel that bypasses the traditional memory subsystem. This new intermediary path allows direct data transfer between cores, eliminating the need for data to pass through memory and thereby reducing latency and improving memory efficiency.
2Speed
If traditional memory-based data transfer is used, then data can be transferred between cores, but bandwidth is limited and transfer speed decreases
Solution Approach 1:
The patent segments the data transfer system into separate dedicated paths: a high-speed core-to-core interface for critical data transfers and the traditional memory interface for general purposes. This segmentation allows the core-to-core path to handle time-sensitive data at high speed and high bandwidth without being constrained by memory subsystem limitations.
Solution Approach 2:
The patent adds a new dimensional communication path between cores by introducing the core-to-core interface as a separate communication dimension alongside the traditional memory-based transfer path. This additional dimension enables parallel data transfer routes, increasing overall system bandwidth and transfer capability.
Data Source
AI summary
Examples herein describe techniques for communicating directly between cores in an array of data processing engines. In one embodiment, the array is a 2D array where each of the data processing engines includes one or more cores. In addition to the cores, the data processing engines can include a memory module (with memory banks for storing data) and an interconnect which provides connectivity between the cores. Using the interconnect, however, can add latency when transmitting data between the cores. In the embodiments herein, the array includes core-to-core communication links that directly connect one core in the array to another core. The cores can use these communication links to bypass the interconnect and the memory module to transmit data directly.