Core-Transistor Voltage Provision Circuit With Fractional Level Shifting
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Solution Overview
Problem
Existing level shifters that utilize only core devices face reliability issues due to high voltage drops across core device terminals, leading to potential damage and operational failures.
Innovation Solution
A voltage provision circuit that generates intermediate signals based on fractional voltages and control signals, using serially coupled inverters to determine the output voltage, ensuring that each core device experiences a voltage drop less than or equal to the fractional voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If level shifters utilize only core devices to improve integration density, then device density increases, but voltage drops across core device terminals increase causing reliability issues
Solution Approach 1:
The circuit is segmented into multiple stages with intermediate voltage nodes. Instead of having core devices handle the full voltage swing directly, the voltage transition is divided into smaller steps through intermediate nodes, reducing the voltage drop across any single core device terminal while maintaining the overall level shifting function.
Solution Approach 2:
I/O devices are introduced as intermediary elements between the core devices and the high-voltage nodes. These I/O devices act as buffers that absorb the high voltage stress, allowing core devices to operate within their safe voltage ranges while still achieving the required level shifting for high-voltage operation.
2Ease of manufacture
If core devices are used in level shifters to maintain device uniformity, then manufacturing simplicity improves, but high voltage drops cause potential damage
Solution Approach 1:
The voltage stress is segmented across multiple devices and nodes. Core devices are distributed throughout the circuit rather than concentrated at high-stress points, and intermediate nodes are strategically placed to limit the voltage drop across any single core device, preventing damage while maintaining manufacturing uniformity.
Solution Approach 2:
I/O devices serve as protective intermediaries that shield core devices from high voltage stress. These intermediary devices are positioned at critical high-voltage nodes, allowing core devices to maintain their uniform design without being exposed to damaging voltage drops.
3Reliability
If fractional voltage generation is implemented to reduce voltage drops, then device stress decreases, but circuit complexity increases
Solution Approach 1:
The circuit employs universal design patterns where I/O devices and intermediate nodes serve multiple functions: they act as voltage buffers, protect core devices from stress, enable level shifting, and provide intermediate voltage references. This multi-functionality reduces the need for additional specialized components, thereby limiting the increase in overall circuit complexity.
Solution Approach 2:
The circuit creates equipotential regions through intermediate nodes that stabilize voltage levels between high-voltage and low-voltage domains. These equipotential nodes reduce voltage drops across core devices by providing stable reference points, achieving stress reduction without requiring complex active regulation circuits.
Data Source
AI summary
A voltage provision circuit includes a first NMOS transistor gated with a first control signal and sourced with a ground voltage, a second NMOS transistor gated with a second control signal complementary to the first control signal and sourced with the ground voltage, a first PMOS transistor sourced with a first supply voltage, a second PMOS transistor sourced with the first supply voltage, and a voltage modulation circuit that is coupled between the first to second PMOS transistors and the first to second NMOS transistors, and is configured to provide a first intermediate signal based on the first and second control signals. The first intermediate signal has a first logic state corresponding to the first supply voltage and a second logic state corresponding to a second supply voltage that is a fraction of the first supply voltage.