Processing Core Voltage Scaling Using a Replicated Critical Path
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Solution Overview
Problem
Modern wireless devices face challenges in conserving battery power due to high power consumption, especially when operating at high clock speeds, as the critical signal path changes with supply voltage variations, making it difficult to establish effective supply voltage scaling without adding unnecessary safety margins that increase power consumption.
Innovation Solution
The implementation of adaptive voltage scaling (AVS) techniques that characterize logic speed and wire speed, determine a target clock frequency, and adjust supply voltage for processing cores using a replicated critical path with programmable delay lines, including various circuit components, to maintain performance while reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If supply voltage is reduced to conserve battery power, then power consumption decreases, but timing requirements of critical signal path may not be met
Solution Approach 1:
The patent implements dynamic voltage scaling by continuously monitoring the critical signal path delay and adjusting the supply voltage in real-time. The voltage is reduced when the critical path delay is within acceptable margins, and increased when timing requirements are at risk, creating a dynamic adaptation to actual circuit behavior rather than using static conservative voltage levels
Solution Approach 2:
The patent employs a feedback mechanism where the actual delay of the critical signal path is measured and used to control the supply voltage. The voltage regulator receives feedback about timing margin status and adjusts voltage accordingly, creating a closed-loop system that optimizes power consumption while ensuring timing requirements are met
2Reliability
If a large safety margin is added to account for process and temperature variations, then reliability is improved, but power consumption increases
Solution Approach 1:
The system dynamically adapts to process and temperature variations by continuously monitoring the actual critical path delay and adjusting voltage accordingly. Instead of using a fixed large safety margin for all conditions, the system only increases voltage when actual measurements indicate timing margins are insufficient, reducing unnecessary power consumption during normal operating conditions
Solution Approach 2:
The patent changes the supply voltage parameter dynamically based on measured timing margins and environmental conditions. By adjusting this critical parameter in response to actual circuit behavior rather than relying on fixed conservative design margins, the system achieves reliable operation across process and temperature variations while minimizing power consumption
3Productivity
If supply voltage is increased to meet timing requirements, then performance is improved, but power consumption increases quadratically
Solution Approach 1:
The system implements dynamic voltage adjustment where the supply voltage is increased only when and where timing requirements are actually at risk. Rather than maintaining high voltage across the entire device for performance, the system locally and temporarily increases voltage only when critical path delay measurements indicate a timing violation is imminent, significantly reducing overall power consumption
Data Source
AI summary
Techniques for adaptively scaling voltage for a processing core are described. In one scheme, the logic speed and the wire speed for the processing core are characterized, e.g., using a ring oscillator having multiple signal paths composed of different circuit components. A target clock frequency for the processing core is determined, e.g., based on computational requirements for the core. A replicated critical path is formed based on the characterized logic speed and wire speed and the target clock frequency. This replicated critical path emulates the actual critical path in the processing core and may include different types of circuit components such as logic cells with different threshold voltages, dynamic cells, bit line cells, wires, drivers with different threshold voltages and/or fan-outs, and so on. The supply voltage for the processing core and the replicated critical path is adjusted such that both achieve the desired performance.