Processor Core Voltage Selection for Energy Efficiency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In multi-processor systems, active processor cores consume higher power than necessary due to lack of per-processor core voltage control, resulting in inefficient energy usage, as most platforms do not have individual voltage-regulator control domains and rely on the highest core Vmin for all cores at a given frequency.
Innovation Solution
Implementing a mechanism to leverage Vmin differences across processor cores by storing per-core Vmin values in non-volatile memory during the High Volume Manufacturing process, allowing the operating system to schedule tasks on the core with the lowest Vmin for energy efficiency, and using energy-aware scheduling schemes to optimize power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If per-processor core voltage control is implemented, then energy efficiency is improved, but device complexity increases due to requiring individual voltage-regulator control domains
Solution Approach 1:
The patent segments the voltage control by creating separate voltage-regulator control domains for different processor core groups. Each domain can independently control voltage for its associated cores based on their specific Vmin characteristics, rather than using a single unified voltage control for all cores. This segmentation enables differentiated voltage management that improves energy efficiency while maintaining manageable system complexity through structured domain separation.
Solution Approach 2:
The patent applies local quality by assigning different voltage levels to different processor core groups based on their individual Vmin characteristics. Each core group receives a customized voltage supply tailored to its specific requirements, allowing cores with lower Vmin to operate at lower voltages and consume less power, while cores requiring higher voltages receive appropriate power levels. This localized voltage optimization resolves the contradiction by enabling energy efficiency improvements without requiring complete per-core voltage control complexity.
2Reliability
If the highest core Vmin is used for all cores at a given frequency, then reliability is maintained, but energy efficiency deteriorates due to unnecessary power consumption on cores with lower Vmin requirements
Solution Approach 1:
The patent implements dynamic voltage adjustment by continuously monitoring and adapting voltage levels for each core group based on their operational requirements and Vmin characteristics. The system dynamically selects appropriate voltage levels from available options, ensuring that each core group operates at the minimum necessary voltage for reliable function. This dynamic approach resolves the contradiction by maintaining reliability through adaptive voltage control while eliminating the waste of using uniformly high voltages for all cores.
Solution Approach 2:
The patent changes the voltage parameter for different core groups based on their specific Vmin characteristics. By storing and utilizing Vmin information for each core group, the system adjusts voltage levels to match actual requirements rather than applying a conservative highest-Vmin setting to all cores. This parameter optimization maintains functional correctness for each core group while significantly reducing overall power consumption.
Data Source
AI summary
A processor core energy-efficiency core ranking scheme akin to a favored core in a multi-core processor system. The favored core is the energy-efficient core that allows an SoC to use the core with the lowest Vmin for energy-efficiency. Such Vmin values may be fused in appropriate registers or stored in NVM during HVM. An OS scheduler achieves optimal energy performance using the core ranking information to schedule certain applications on the core with lowest Vmin. A bootstrap flow identifies a bootstrap processor core (BSP) as the most energy efficiency core of the SoC and assigns that core the lowest APIC ID value according to the lowest Vmin. Upon reading the fuses or NVM, the microcode/BIOS calculates and ranks the cores. As such, microcode/BIOS calculates and ranks core APIC IDs based on efficiency around LFM frequencies. Based on the calculated and ranked cores, the microcode or BIOS transfers BSP ownership to the most efficiency core.