Processor Core Wake-Up Control During Power Failure
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Solution Overview
Problem
In legacy systems, power failures cause all processor cores to transition from a deep sleep state to an awake state, resulting in significant power consumption and non-negligible time consumption.
Innovation Solution
Implementing interrupt control logic to manage core states during power failures, ensuring only a subset of processor cores transition to the awake state, while others remain in a sleep state, thereby reducing unnecessary power usage and time consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all processor cores are woken from deep sleep state to awake state upon power failure, then system reliability is improved, but power consumption increases significantly and time consumption increases
Solution Approach 1:
The system segments the processor cores into two groups: a first plurality of cores that are woken up upon power failure, and a second plurality of cores that remain in deep sleep state. This segmentation allows the system to maintain reliability through the first group of cores while reducing overall power consumption by keeping the second group dormant.
Solution Approach 2:
Instead of waking up all processor cores (excessive action), the system wakes up only a partial subset of cores (first plurality) that is sufficient to handle power failure tasks. This partial action reduces power consumption while still achieving the necessary system response to power failure events.
2Reliability
If all processor cores are woken from deep sleep state to awake state upon power failure, then system reliability is improved, but time consumption increases
Solution Approach 1:
The system segments the processor cores into two groups: a first plurality of cores that are woken up upon power failure, and a second plurality of cores that remain in deep sleep state. This segmentation allows the system to maintain reliability through the first group of cores while reducing overall wake-up time by keeping the second group dormant.
Solution Approach 2:
Instead of waking up all processor cores (excessive action), the system wakes up only a partial subset of cores (first plurality) that is sufficient to handle power failure tasks. This partial action reduces the total time required for core state transitions while still achieving the necessary system response to power failure events.
3Use of energy by moving object
If a subset of processor cores remains in sleep state during power failure, then power consumption is reduced, but system complexity increases
Solution Approach 1:
The core controller serves multiple functions: it manages the power state transitions of processor cores, detects power failure conditions, and selectively wakes up appropriate core groups. This multi-functionality reduces the need for additional dedicated components, thereby limiting the increase in system complexity while enabling selective core wake-up.
Solution Approach 2:
The system uses its existing core controller and interrupt logic to manage the selective wake-up process without requiring external control mechanisms. The core controller autonomously determines which cores to wake based on power failure detection, reducing the need for additional control hardware or software complexity.
Data Source
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AI summary
Embodiments herein relate to a power control unit (PCU) of an electronic device. The PCU may be configured to receive a power failure interrupt from an interrupt control block of the electronic device. The power failure interrupt may be generated based on or related to a power failure of the electronic device. In response to receipt of the power failure interrupt, and when a threshold number of processor cores related to the power failure is different than a number of awake processor cores of a set of processor cores of the electronic device, the PCU may transition a subset of processor cores of the set of processor cores to an awake state or a sleep state so that the number of awake processor cores is same as the threshold number of processor cores. Other embodiments may be described and/or claimed.