Core Wrapper Optimization via Shared Flip-Flop Reuse
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Solution Overview
Problem
Current design for test (DFT) methodologies in integrated circuits face area and timing issues due to the use of dedicated wrapper cells, which adversely affect the design of system-on-chip (SOC) and application-specific integrated circuit (ASIC) designs, especially when large numbers of functional shift registers are present.
Innovation Solution
Optimizing core wrappers by increasing the use of shared wrapper cells instead of dedicated wrapper cells, even in the presence of shift registers, to reduce area overhead and improve timing performance, by identifying and reusing existing flops as shared wrapper cells and splitting shift registers when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated wrapper cells are used in core wrappers, then test access functionality is ensured, but area overhead increases and timing performance deteriorates
Solution Approach 1:
The patent applies universality by enabling shared wrapper cells to serve multiple functions: they act as both functional flip-flops in the normal operating mode and as wrapper cells providing test access in scan mode. This multi-functionality eliminates the need for separate dedicated wrapper cells, thereby reducing area overhead while maintaining test access functionality.
Solution Approach 2:
The patent merges the functional flip-flops with wrapper cell functionality by allowing shared wrapper cells to be part of both the functional logic and the scan chains. This combining approach integrates test access capabilities into existing functional elements rather than adding separate dedicated wrapper structures.
2Reliability
If dedicated wrapper cells are used in core wrappers, then test access functionality is ensured, but timing performance deteriorates
Solution Approach 1:
Shared wrapper cells perform dual roles as functional elements and test access points, eliminating the additional timing overhead introduced by dedicated wrapper cells. The shared cells are already part of the functional timing paths, so reusing them for test access does not add extra timing delays.
Solution Approach 2:
By merging functional flip-flops with wrapper cell functionality, the patent eliminates the separate timing paths that would be introduced by dedicated wrapper cells. The shared wrapper cells operate within the existing functional timing constraints, avoiding additional timing penalties.
3Area of stationary object
If shared wrapper cells are used instead of dedicated wrapper cells, then area overhead is reduced, but design complexity increases due to shift register management
Solution Approach 1:
The patent applies segmentation by dividing shift registers into segments that can be independently configured for functional or test mode operation. This segmentation allows shared wrapper cells to be properly managed within the scan chain structure, reducing the complexity burden of managing large monolithic shift registers.
Solution Approach 2:
The patent performs preliminary configuration of shared wrapper cells during the design phase, establishing their dual functionality before implementation. This preliminary action includes configuring the scan chain connections and wrapper cell assignments, which simplifies the overall design management by resolving complexity issues upfront rather than during operation.
4Area of stationary object
If shared wrapper cells are used in the presence of shift registers, then area efficiency is improved, but shift register management becomes more complex
Solution Approach 1:
The patent segments shift registers to work harmoniously with shared wrapper cells, creating a structured approach where shift register segments are properly integrated with the shared wrapper cell architecture. This segmentation enables efficient area utilization while managing the complexity of coordinating shift register operations with shared wrapper functionality.
Data Source
AI summary
According to certain aspects, the present embodiments relate to optimizing core wrappers in an integrated circuit to facilitate core-based testing of the integrated circuit. In some embodiments, an integrated circuit design flow is adjusted so as to increase the use of shared wrapper cells in inserted core wrappers, and to reduce the use of dedicated wrapper cells in such core wrappers, thereby improving timing and other integrated circuit design features. In these and other embodiments, the increased use of shared wrapper cells is performed even in the presence of shift registers in the integrated circuit design.