Core Wrapping With Embedded Wrapped Cores Using Nested Scan Chains

The patent implements multiple levels of nested scan chains where an outer scan chain wraps the entire die and nested scan chains wrap embedded cores within the die. This nested structure allows test patterns to propagate through multiple hierarchical levels simultaneously, maintaining full coverage of interface logic while accommodating the complex nested wrapped core design structure.

The patent segments the test architecture into multiple independent scan chain levels (outer scan chain and nested scan chains), each capable of independently controlling and observing specific hierarchical levels. This segmentation allows different portions of the design to be tested independently while maintaining overall coverage, resolving the contradiction between handling complex nested structures and maintaining test coverage.

The patent creates a nested scan chain architecture where outer scan chains at the die level and inner scan chains at the embedded core level work together. The outer scan chain provides control and observation capability for interface logic connecting embedded cores to the rest of the die, while inner scan chains handle the embedded cores themselves. This nested approach enables both hierarchical testing capability and interface logic observability simultaneously.

The patent introduces scan chain isolation wrappers as intermediary structures between embedded wrapped cores and the outer scan chain. These wrappers provide the necessary control and observation interfaces for the interface logic, acting as mediators that enable the outer scan chain to control and observe interface logic while the embedded cores maintain their own nested scan chain structures for hierarchical testing.

The patent segments the test generation and verification process into multiple parallel operations across different scan chain levels. Multiple test patterns can be generated and applied simultaneously at different hierarchical levels (outer die level and inner embedded core levels), significantly reducing overall test generation time and verification turnaround time compared to sequential single-level testing approaches.

The patent implements preliminary configuration of nested scan chains and isolation wrappers during the design phase, establishing the test infrastructure beforehand. This preliminary action enables rapid test pattern generation and execution during verification, reducing the time required for test generation and verification turnaround by having the hierarchical test structure already in place rather than creating it during the testing phase.