Coreless Antenna Package Layout for Lower Cost and Warpage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor packages with integrated antennas face challenges such as high costs due to cored substrates, reduced antenna efficiency from solid ground planes, and substrate warpage during fabrication and reliability tests.
Innovation Solution
The integration of asymmetric build-up layer counts and dummification elements in semiconductor packages, which reduce layer count, enhance antenna gain and efficiency, and provide mechanical robustness, while using both sides of a temporary substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cored substrates are used in semiconductor packages, then antenna performance is improved, but manufacturing cost increases
Solution Approach 1:
The patent replaces expensive cored substrates with temporary substrates that are removed after fabrication. The temporary substrate serves its purpose during manufacturing but is discarded afterward, eliminating the need for costly permanent cored substrates while maintaining antenna performance during the critical fabrication and testing phases.
Solution Approach 2:
The patent changes the substrate parameter from permanent (cored substrate) to temporary (removable substrate). This parameter change allows the use of cheaper materials during fabrication that can be easily removed, replacing the need for expensive permanent cored substrates while maintaining the required antenna performance characteristics.
2Ease of manufacture
If solid ground planes are used in semiconductor packages, then manufacturing is simplified, but antenna efficiency decreases
Solution Approach 1:
The patent applies local quality by creating asymmetric build-up layers with different thicknesses on opposite sides of the temporary substrate. This localized variation in layer thickness provides the necessary mechanical robustness and electrical performance in specific areas without requiring solid ground planes across the entire structure, thereby maintaining antenna efficiency while simplifying manufacturing.
3Reliability
If asymmetric build-up layer counts are used, then antenna efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The patent deliberately introduces asymmetry through asymmetric build-up layer counts on opposite sides of the temporary substrate. This asymmetric structure improves antenna efficiency by creating the necessary electrical characteristics while the symmetry of the overall fabrication process (applying the same steps to both sides) keeps manufacturing complexity manageable.
4Ease of manufacture
If temporary substrates are used, then manufacturing cost is reduced, but substrate warpage occurs during fabrication
Solution Approach 1:
The patent applies preliminary action by forming asymmetric build-up layers on the temporary substrate before final assembly. This preliminary structuring provides mechanical robustness that prevents warpage during subsequent fabrication and reliability testing steps, allowing the use of cost-effective temporary substrates without suffering from warpage issues.
Solution Approach 2:
The patent changes the physical parameters of the build-up layers (asymmetric thickness distribution) to provide mechanical support that counteracts warpage. This parameter change transforms the temporary substrate from a warpage-prone structure to a mechanically robust platform that maintains stability throughout fabrication and testing.
Data Source
AI summary
In various embodiments, disclosed herein are systems and methods directed to the fabrication of a coreless semiconductor package (e.g., a millimeter (mm)-wave antenna package) having an asymmetric build-up layer count that can be fabricated on both sides of a temporary substrate (e.g., a core). The asymmetric build-up layer count can reduce the overall layer count in the fabrication of the semiconductor package and can therefore contribute to fabrication cost reduction. In further embodiments, the semiconductor package (e.g., a millimeter (mm)-wave antenna packages) can further comprise dummification elements disposed near one or more antenna layers. Further, the dummification elements disposed near one or more antenna layers can reduce image current and thereby increasing the antenna gain and efficiency.