Coreless Antenna Package Layout for Lower Warpage and Higher Gain
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Solution Overview
Problem
Existing semiconductor packages with integrated antennas face challenges such as high cost due to metal voiding requirements, reduced antenna efficiency from solid ground planes, and substrate warpage during fabrication and reliability tests, particularly in millimeter-wave applications.
Innovation Solution
The integration of asymmetric build-up layer counts and dummification elements in semiconductor packages, which reduce layer count, minimize surface current, enhance mechanical robustness, and improve antenna gain and efficiency, while maintaining mechanical stability and reducing warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solid ground planes are used in semiconductor packages, then antenna efficiency is reduced due to surface current, but structural support is improved
Solution Approach 1:
The ground plane is segmented into discrete ground vias arranged in a grid pattern rather than a solid continuous plane. This segmentation allows the antenna elements to operate without excessive surface current while the distributed ground vias provide sufficient structural support and electrical grounding.
Solution Approach 2:
Different regions of the package have different properties: the areas beneath antenna elements use a hollow or segmented structure to minimize surface current and maximize antenna efficiency, while other regions maintain solid ground planes for structural support and electrical grounding.
2Ease of manufacture
If metal voiding requirements are implemented, then cost is reduced, but manufacturing complexity increases
Solution Approach 1:
The ground plane is divided into discrete ground vias that can be formed using standard via fabrication processes, eliminating the need for complex metal voiding operations while reducing material usage and cost.
Solution Approach 2:
The patent eliminates unnecessary metal structures (voiding) in specific regions where they would interfere with antenna performance, while retaining metal in regions where it provides structural or electrical function, optimizing both cost and performance.
3Device complexity
If asymmetric build-up layer counts are used, then layer count is reduced and cost is decreased, but mechanical stability may be compromised
Solution Approach 1:
The package uses asymmetric build-up layer counts on different sides of the substrate, with fewer layers on the antenna side and more layers on the opposite side. This asymmetric design reduces overall layer count and cost while the distributed ground via structure provides mechanical stability to compensate for the asymmetry.
4Reliability
If dummification elements are added, then antenna gain and efficiency are improved, but device complexity increases
Solution Approach 1:
The dummification elements are merged with the ground via structure, serving dual purposes: providing electrical grounding and acting as dummification elements to improve antenna gain and efficiency. This integration avoids adding separate components and minimizes device complexity.
Data Source
AI summary
In various embodiments, disclosed herein are systems and methods directed to the fabrication of a coreless semiconductor package (e.g., a millimeter (mm)-wave antenna package) having an asymmetric build-up layer count that can be fabricated on both sides of a temporary substrate (e.g., a core). The asymmetric build-up layer count can reduce the overall layer count in the fabrication of the semiconductor package and can therefore contribute to fabrication cost reduction. In further embodiments, the semiconductor package (e.g., a millimeter (mm)-wave antenna packages) can further comprise dummification elements disposed near one or more antenna layers. Further, the dummification elements disposed near one or more antenna layers can reduce image current and thereby increasing the antenna gain and efficiency.