Coreless Chip Carrier with Asymmetric Insulating Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing manufacturing processes for flip chip substrates, such as FCCSP and FCBGA, require thick core substrates for mechanical stability, leading to increased material and processing costs, as well as reduced telecommunications bandwidth due to lower drilling density, and high thermal expansion coefficients that affect reliability.
Innovation Solution
A coreless chip carrier design using a first structure layer with a low thermal expansion coefficient glass fiber resin and a second structure layer with bismaleimide-triazine resin or Ajinomoto build-up film, featuring conductive through holes and patterned circuit layers, which reduces material usage and manufacturing steps while maintaining thermal stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a thick core substrate is used to maintain mechanical stability, then the carrier stability is improved, but the manufacturing cost and material usage increase
Solution Approach 1:
The patent removes the thick core substrate from the traditional carrier structure, extracting only the essential function of providing mechanical support. This is achieved by using a thin substrate combined with build-up layers that have appropriate mechanical properties, eliminating the need for expensive thick core materials while maintaining carrier stability during manufacturing processes.
Solution Approach 2:
The patent employs composite material structures where build-up layers with specific mechanical properties are constructed on top of a thin substrate. These composite structures provide the necessary mechanical support and stability without requiring a thick core substrate, thereby reducing material costs and improving manufacturing efficiency.
2Stability of the object's composition
If a thick core substrate is used to maintain mechanical stability, then the carrier stability is improved, but the drilling density and telecommunications bandwidth are reduced
Solution Approach 1:
By removing the thick core substrate, the patent enables higher drilling density in the build-up layers. The absence of a thick core allows for more closely spaced holes and better signal transmission paths, directly improving telecommunications bandwidth while maintaining carrier stability through the engineered build-up layer structure.
3Stability of the object's composition
If build-up layers are added below the core substrate to maintain stability, then the carrier stability is improved, but the manufacturing time and material costs increase
Solution Approach 1:
The patent eliminates the need for symmetric build-up layers below the substrate by removing the thick core substrate requirement. Stability is achieved through controlled build-up layers on one side only, significantly reducing the number of manufacturing steps and material usage while maintaining adequate carrier stability throughout the manufacturing process.
4Temperature
If glass fiber is not contained in ABF material to reduce thermal expansion coefficient, then the thermal stability is improved, but the material selection is limited
Solution Approach 1:
The patent applies local quality by selecting ABF material without glass fiber specifically for the build-up layers where low thermal expansion is critical, while maintaining flexibility in material selection for other carrier components. This localized material optimization achieves thermal stability where needed without constraining overall material choices for the complete carrier structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces material and processing costs, enhances manufacturing efficiency, and improves thermal stability, facilitating reliable chip packaging with reduced thermal expansion mismatch and eliminating the need for thick core substrates.
Implementation Method 1
A thermal expansion coefficient of the first insulating layer is between 2 ppm/°C. and 5 ppm/°C.
Implementation Method 2
a thermal expansion coefficient of the second insulating layer is equal to or greater than the thermal expansion coefficient of the first insulating layer
Data Source
AI summary
A chip carrier and a manufacturing method thereof are provided. The chip carrier includes a first structure layer and a second structure layer. The first structure layer has at least one opening and includes at least one first insulating layer. A thermal expansion coefficient of the first insulating layer is between 2 ppm/° C. and 5 ppm/° C. The second structure layer is disposed on the first structure layer and defines at least one cavity with the first structure layer. The second structure layer includes at least one second insulating layer, and a thermal expansion coefficient of the second insulating layer is equal to or greater than the thermal expansion coefficient of the first insulating layer.