Coreless Circuit Board Pad Design for Thin Packaging
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Solution Overview
Problem
The challenge is to minimize the thickness of a circuit board while ensuring bonding reliability between a die and a silicon capacitor, as the width of the pad on the silicon capacitor and the bump pad on the circuit board differ, and existing core substrate thickness limits further miniaturization.
Innovation Solution
A circuit board design with an insulating layer, a circuit wire, and a circuit element, where the first conductive pad protrudes above the insulating layer and the element pad is embedded, allowing for a wider element pad and adjusted adhesive member thickness to secure reliable connections, and a manufacturing method involving sequential layer formation and etching to create a coreless substrate with embedded passive elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the die and silicon capacitor are directly connected with different pad widths, then the path between die and capacitor is reduced, but bonding reliability between pads deteriorates
Solution Approach 1:
The patent introduces a first conductive pad as an intermediary component between the die bump pad and the silicon capacitor element pad. This intermediate pad serves as a mediator that bridges the width mismatch between the two components, enabling reliable bonding while maintaining the shortened power delivery path. The first conductive pad is wider than both the bump pad and element pad, providing sufficient bonding area for both connections.
2Strength
If a core member is used in the circuit board, then structural strength is maintained, but the thickness of the circuit board cannot be minimized
Solution Approach 1:
The patent extracts and removes the core member from the circuit board structure, transitioning to a coreless substrate design. The circuit board is constructed using only insulating layers without a central core, which enables significant thickness reduction while maintaining structural integrity through the layered insulating material configuration.
3Reliability
If the element pad width is made wider than the bump pad width, then bonding reliability is improved, but the pad alignment complexity increases
Solution Approach 1:
The patent resolves the alignment complexity by transitioning from a two-dimensional planar alignment problem to a three-dimensional spatial arrangement. The first conductive pad is positioned at a different height level (Z-dimension) between the bump pad and element pad, with its upper surface protruding above the insulating layer while its lower surface is embedded. This vertical dimension provides alignment tolerance and simplifies the bonding process despite the width mismatch.
Data Source
AI summary
The present disclosure provides a circuit board including: an insulating layer; a circuit wire disposed in a first area inside the insulating layer, a first conductive pad connected to the circuit wire and having an upper surface protruding above an upper surface of the insulating layer and a lower surface embedded in the insulating layer; and a circuit element disposed to have a boundary surface parallel to the upper surface of the insulating layer in a second area different from the first area inside the insulating layer and including an element pad.