Coreless EMIB Substrates for Overlay Accuracy and Low Warpage
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Solution Overview
Problem
Existing semiconductor packaging technologies face challenges in achieving high-accuracy and high-density embedded interconnect bridges due to issues like warpage, stringent overlay requirements, and increased bump thickness variation, which lead to manufacturing costs and yield reduction.
Innovation Solution
The solution involves building critical layers directly on a rigid and flat carrier to minimize warpage and enable direct alignment, using a coreless construction with organic or glass cores to maintain panel flatness, and implementing etch stop layers to control laser drilling and patterning, thereby reducing residual stress and improving overlay accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If indirect alignment is used for upper layers in build-up processes, then manufacturing flexibility is improved, but overlay accuracy deteriorates due to artificially stringent overlay requirements
Solution Approach 1:
The patent applies preliminary action by pre-forming the carrier with integrated alignment features and direct alignment mechanisms before the build-up process. The carrier is prepared in advance with precise geometric features that enable direct alignment, eliminating the need for indirect alignment methods and their associated overlay errors.
Solution Approach 2:
The patent introduces the carrier as an intermediary element that mediates between the build-up layers and the final assembly. The carrier serves as a stable reference platform with integrated alignment features, acting as a mediator that enables precise direct alignment without the complications of indirect alignment methods.
2Device complexity
If critical layers are built last on already warped panels, then manufacturing sequence is simplified, but overlay accuracy deteriorates due to warpage-induced distortion
Solution Approach 1:
The patent applies preliminary anti-action by pre-compensating for warpage through the rigid carrier structure. The carrier is designed to counteract warpage forces before they can affect the critical layers, maintaining panel flatness throughout the build-up process and eliminating the need to build critical layers last on warped panels.
Solution Approach 2:
The patent introduces dynamic stress distribution through the carrier design, which adapts to and counteracts warpage forces in real-time. The carrier's rigid structure dynamically resists warpage-induced distortion, maintaining a stable platform for precise layer formation regardless of the manufacturing sequence.
3Quantity of substance
If tighter pitches are implemented in FLI and BDL, then integration density is improved, but manufacturing yield deteriorates due to challenging high-density patterning
Solution Approach 1:
The patent replaces complex mechanical alignment systems with direct alignment mechanisms integrated into the carrier. This substitution enables precise patterning at tighter pitches by eliminating cumulative alignment errors from multiple mechanical alignment steps, thereby improving manufacturing yield at high integration densities.
Solution Approach 2:
The patent changes the fundamental alignment parameter from indirect multi-step alignment to direct single-step alignment. This parameter change enables tighter pitches to be achieved with maintained yield by reducing the number of alignment operations and their associated error accumulation.
4Adaptability or versatility
If multiple build-up layers of plated metal and dielectrics are formed, then interconnect functionality is improved, but bump thickness variation increases due to metal density differences and via recesses
Solution Approach 1:
The patent applies preliminary action by pre-forming the carrier with integrated bump structures and uniform metal distribution before the build-up process. This preliminary preparation ensures that subsequent plated metal layers and dielectric layers are formed on a uniform foundation, reducing metal density differences and via recess variations that lead to bump thickness variation.
Solution Approach 2:
The patent introduces homogeneity through the carrier design, which provides a uniform base for metal plating and dielectric formation. The carrier's integrated structures ensure consistent metal distribution and via depth across the substrate, leading to uniform bump thickness despite the presence of multiple build-up layers with varying interconnect functionalities.
Data Source
AI summary
Embodiments include semiconductor packages and method of forming the semiconductor packages. A semiconductor package includes a plurality of conductive layers over a package substrate. The conductive layers include a first conductive layer and first-level interconnects (FLIs) in the package substrate. The semiconductor package also includes a solder resist that surrounds the FLIs, where the solder resist has a top surface that is substantially coplanar to top surfaces of the FLIs, a bridge coupled directly to the first conductive layer with solder balls, where the first conductive layer is coupled to the FLIs, and a dielectric over the conductive layers, the bridge, and the solder resist of the package substrate. The bridge may be an embedded multi-die interconnect bridge (EMIB). The first conductive layer may include first conductive pads and second conductive pads. The FLIs may include first conductive vias, second conductive vias, diffusion layers, and third conductive pads.