Coreless Interposer Substrate Fabrication via Carrier Removal
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Solution Overview
Problem
The existing interposer substrates for package on package (PoP) face challenges such as high fabrication complexity and cost, limited thickness, conductivity issues due to residual conducting layers, and restricted line width/line space design, leading to low product yield and reliability problems.
Innovation Solution
A coreless interposer substrate is fabricated using a carrier-based method that eliminates the formation of vias, allowing for a simpler and cost-effective process, enabling finer line width/line space designs and preventing conductivity issues by directly forming external connection pillars without additional conducting layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vias are formed in the plate to create traditional interposer substrate, then electrical connection between layers is achieved, but fabrication complexity and cost increase significantly
Solution Approach 1:
The patent removes the plate substrate entirely from the traditional interposer structure, extracting only the essential wiring layer and insulation layer components. This eliminates the need to form vias through a plate, significantly simplifying the fabrication process while maintaining electrical connection functionality between stacked packages.
Solution Approach 2:
The interposer substrate is segmented into separate functional layers: a wiring layer containing conductive traces, and an insulation layer with through-holes for mechanical support and alignment. This segmentation allows the wiring layer to be formed independently on a carrier before being integrated with the insulation layer, avoiding the complexity of forming vias in a solid plate.
2Reliability
If additional conducting layers are formed for electroplating copper pillars, then copper pillars can be formed, but residual conducting layers remain causing conductivity issues and short circuits
Solution Approach 1:
The wiring layer is formed preliminarily on a carrier substrate before the insulation layer is applied. This preliminary formation of the wiring layer with its conductive traces allows subsequent electroplating of copper pillars to occur directly on these pre-formed traces without requiring additional conducting layers, thereby preventing residual layer issues.
Solution Approach 2:
The carrier substrate serves as a temporary, disposable platform for forming the wiring layer. After the wiring layer is formed and integrated with the insulation layer, the carrier is removed, taking with it any temporary conducting layers or support structures. This eliminates the problem of residual conducting layers that would otherwise remain and cause conductivity issues.
3Length of stationary object
If plate thickness is reduced to enable thinner PoP products, then product thickness decreases, but plate becomes fragile and prone to damage
Solution Approach 1:
The interposer substrate uses a composite structure combining an insulation layer material (such as epoxy or ceramic) with integrated wiring layer traces. This composite approach provides both mechanical strength and electrical functionality, allowing the substrate to be made thinner without sacrificing structural integrity, as the insulation layer material inherently provides strength without requiring thick metal plate construction.
4Quantity of substance
If line width and line space are reduced to increase layout density, then more contacts can be accommodated, but fabrication precision requirements increase
Solution Approach 1:
The wiring layer patterns are formed by copying or transferring designs from the carrier substrate using standard PCB fabrication techniques such as photolithography. This copying approach allows for precise replication of fine line width and line space patterns without requiring ultra-precision fabrication equipment, as the patterns are transferred from a master template on the carrier.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a more reliable, cost-effective interposer substrate with increased layout density and improved conductivity, reducing the risk of short circuits and enabling thinner, more reliable PoP products with higher pin count and finer spacing.
Implementation Method 1
a copper pillar 14 is formed on the conductive pad 150 in an electroplating way
Data Source
AI summary
A method for fabricating an interposer substrate is provided, including forming a wiring layer on a carrier, forming an insulating layer on the carrier, forming on the wiring layer a wiring build-up layer structure that is electrically connected to the wiring layer, forming on the wiring build-up layer structure external connection pillars that are electrically connected to the wiring build-up layer structure, and removing the carrier, with the wiring layer is exposed from a surface of the insulating layer. The fabrication process of the via can be bypassed in the fabrication process by forming coreless interposer substrate on the carrier, such that the overall cost of the fabrication process can be decreased, and the fabrication process is simple. This invention further provides the interposer substrate.