Coreless Laminated Substrate Fabrication via Sacrificial Carrier
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current core-less substrate technologies face challenges in achieving cost-effectiveness, high performance, and planarity, particularly in multilayer structures, due to issues with thin film interconnects, warping, and unbalanced residual stresses, which affect the reliability and yield of IC packaging.
Innovation Solution
A novel manufacturing technique that fabricates a self-supported, flat, core-less laminated substrate with solid copper vias and fiber-reinforced dielectric materials, using a sacrificial carrier method to balance residual stresses and ensure planarity, allowing for simultaneous co-fabrication of layers on both sides of a central substructure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If thin film interconnects are used in core-less substrate, then device complexity is reduced and manufacturing is simplified, but reliability deteriorates due to warping and unbalanced residual stresses
Solution Approach 1:
The patent applies asymmetry by implementing a symmetrical multilayer structure where identical layers are positioned on both sides of the central core-less substrate. This symmetrical arrangement balances residual stresses and prevents warping, resolving the reliability issue while maintaining the simplicity of the core-less design. The structure comprises alternating conductive and insulating layers arranged symmetrically around the central substrate region.
Solution Approach 2:
The patent segments the substrate into multiple distinct layers including conductive layers, insulating layers, and a central core-less region. This segmentation allows each layer to be optimized independently for its specific function while maintaining overall structural integrity. The conductive layers are separated by insulating layers, creating a modular structure that reduces complexity while ensuring reliability through proper stress distribution.
2Manufacturing precision
If multilayer structures are fabricated simultaneously on both sides of central substructure, then manufacturing precision and planarity are improved, but device complexity increases
Solution Approach 1:
The patent merges the fabrication processes for both sides of the substrate by simultaneously forming corresponding layers on opposite sides of the central substructure. This combined approach ensures symmetrical stress distribution and improved planarity while efficiently utilizing manufacturing resources. The simultaneous fabrication of matching layers on both sides reduces the overall manufacturing complexity compared to sequential processing.
Solution Approach 2:
The patent employs preliminary actions by first forming the central core-less substructure before building up the multilayer structure on both sides. This preliminary formation of the central region provides a stable foundation that guides subsequent layer deposition and ensures proper alignment. The preliminary preparation of the central substructure enables precise control over final substrate planarity while streamlining the overall fabrication sequence.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The technique achieves high-yield, cost-effective, and reliable multilayer interconnect support structures with minimal thermal impedance and electrical signal loss, suitable for advanced IC packaging applications, including Flip Chip and Wire Bond assembly processes.
Implementation Method 1
fiber-reinforced dielectric materials
Implementation Method 2
balance residual stresses and ensure planarity
Implementation Method 3
solid copper vias and fiber-reinforced dielectric materials
Implementation Method 4
minimal thermal impedance
Data Source
AI summary
A method of fabricating a free standing membrane including via array in a dielectric for use as a precursor in the construction of superior electronic support structures, includes the steps of fabricating a membrane of conductive vias in a dielectric surround on a sacrificial carrier, and detaching the membrane from the sacrificial carrier to form a free standing laminated array. An electronic substrate based on such a free standing membrane may be formed by thinning and planarizing laminated array, followed by terminating.