Coreless Package Structure Using CTE-Balanced Interconnection Layers
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Solution Overview
Problem
The existing semiconductor chip integration technologies, such as Intel's embedded multi-die interconnect bridge (EMIB), face challenges with high costs and structural instability due to the need for an organic core interconnect substrate, which complicates flip-chip package operations and increases production costs.
Innovation Solution
A package structure with a coreless design comprising an embedded component circuit structure layer, a signal interconnection structure layer, and a power structure layer, where the signal interconnection structure layer has a higher coefficient of thermal expansion than the electronic and power structure layers, ensuring structural stability and reducing substrate thickness and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an organic core interconnect substrate is used for chip integration, then electrical connection between adjacent chips is achieved, but production costs increase and structural stability deteriorates
Solution Approach 1:
The patent removes the organic core interconnect substrate from the chip integration structure, replacing it with a simplified carrier-based architecture. The carrier serves as the foundation without requiring complex organic substrate construction, thereby reducing device complexity while maintaining electrical connection functionality through alternative interconnection methods.
Solution Approach 2:
The patent divides the integration structure into distinct functional layers: the carrier, the first substrate containing the first chip, and the second substrate containing the second chip. This segmentation allows each component to be optimized independently, reducing overall system complexity while achieving the required electrical interconnections through controlled vias and conductive structures.
2Productivity
If an organic core interconnect substrate is embedded late in substrate construction, then high-density interconnection is achieved, but surface flatness deteriorates and costs increase
Solution Approach 1:
The patent performs preliminary actions by establishing the carrier and first substrate structure before adding the second substrate. The carrier is prepared in advance with appropriate flatness characteristics, and the first substrate is attached to it before the second substrate is introduced. This sequence ensures surface flatness is maintained throughout the construction process while still achieving high-density interconnections through the designed via and trace structures.
3Adaptability or versatility
If an organic core interconnect substrate is used, then chip integration is achieved, but production costs increase
Solution Approach 1:
The patent replaces the expensive organic core interconnect substrate with a more cost-effective carrier structure. The carrier serves its purpose as a temporary or permanent mounting platform without requiring the high-cost organic substrate materials and complex manufacturing processes, thereby reducing production costs while maintaining chip integration capability.
Solution Approach 2:
The patent changes the material and structural parameters of the base substrate from organic core interconnect substrate to a simpler carrier material. This parameter change reduces manufacturing complexity and cost while maintaining the essential functionality of chip integration through alternative interconnection methods using vias and conductive traces.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The package structure achieves improved structural stability and reduced production costs by maintaining thermal balance during temperature changes, minimizing warpage, and enabling high-density interconnections without the need for an organic core interconnect substrate.
Implementation Method 1
A coefficient of thermal expansion of the signal interconnection structure layer is higher than a coefficient of thermal expansion of the electronic component layer and a coefficient of thermal expansion of the power structure layer
Data Source
AI summary
A package structure includes an embedded component circuit structure layer, a signal interconnection structure layer, a power structure layer, and an electronic component layer. The embedded component circuit structure layer includes at least one embedded component and has a first surface and a second surface opposite to each other. The signal interconnection structure layer is disposed on the first surface and is electrically connected to the embedded component circuit structure layer. The power structure layer is disposed on and electrically connected to the signal interconnection structure layer. The electronic component layer includes a plurality of electronic components, is disposed on the second surface, and is electrically connected to the embedded component circuit structure layer. A coefficient of thermal expansion of the signal interconnection structure layer is higher than a coefficient of thermal expansion of the electronic component layer and a coefficient of thermal expansion of the power structure layer.