Coreless Substrate Package Using Edge Stiffener Ring to Limit Warpage
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Solution Overview
Problem
Conventional semiconductor packaging with a core substrate faces challenges in warpage control and increased thickness, which affects electrical performance and profile, particularly in large coreless substrate packages greater than 45 mm×45 mm.
Innovation Solution
A coreless substrate package design featuring a function silicon die mounted on a coreless substrate with an encapsulant, underfill material, stiffener ring, and gap fill material, eliminating the need for a permanent core structure and utilizing insulating and conductive layers like Ajinomoto Build-up Film and copper, with C4 bumps and BGA ball pads for electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a core material is used in the package substrate, then the substrate provides structural support and routing capability, but the package thickness increases and warpage control becomes difficult
Solution Approach 1:
The patent removes the core material from the package substrate, extracting the problematic element that caused increased thickness and warpage issues. The substrate is redesigned as a coreless structure with build-up layers formed directly on the carrier wafer, eliminating the need for a permanent core while maintaining routing capability through the build-up layers.
Solution Approach 2:
The substrate structure is segmented into distinct functional layers: carrier wafer, first build-up layer with first routing, second build-up layer with second routing, and connection pads. This segmentation allows each layer to perform its specific function without requiring a thick core, enabling thin profile while maintaining structural support and routing capability.
2Ease of manufacture
If a core material is used in the package substrate, then routing between layers is enabled, but the routing length increases due to substrate thickness
Solution Approach 1:
The patent transitions from planar routing within a thick core to three-dimensional routing through multiple thin build-up layers. The first and second routing layers are stacked vertically, allowing signals to travel shorter distances by utilizing the vertical dimension. This layered approach reduces routing length while maintaining comprehensive connectivity capability.
3Length of stationary object
If a coreless substrate design is used, then package thickness is reduced and warpage is controlled, but additional structural elements like stiffener rings are required
Solution Approach 1:
The stiffener ring is strategically placed at the periphery of the coreless substrate where it is most needed for structural support. This localized reinforcement provides the necessary rigidity and warpage control only at the edges, while the central area remains thin and flexible. The stiffener ring's position and dimensions are optimized to provide maximum structural benefit with minimum added complexity.
4Productivity
If the function silicon die is mounted with active front side facing downward, then electrical connection density is improved, but the die orientation and packaging process become more complex
Solution Approach 1:
The patent inverts the conventional die mounting orientation by placing the active front side of the function silicon die facing downward toward the coreless substrate, rather than the conventional upward orientation. This inversion enables direct electrical connection between the die and substrate, increasing connection density. The packaging process is accordingly adapted to accommodate this inverted mounting approach.
Data Source
AI summary
A coreless substrate package includes a coreless substrate; a package device mounted on a coreless substrate; an underfill material filling into a space between the package device and the coreless substrate; a stiffener ring disposed on a top surface of the coreless substrate along perimeter of the coreless substrate; and a gap fill material disposed in a gap between the stiffener ring and the package device.