Coreless Organic Package Layout With EMIB and Protected Magnetic Inductors
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Solution Overview
Problem
Current coreless organic semiconductor packages face limitations in high-speed Input/Output (I/O) density and power delivery efficiency due to constraints in first-level interconnect configurations and exposure issues with wet chemistries during manufacturing, particularly with resin bleed-out and metallization.
Innovation Solution
The integration of embedded multi-die interconnect bridges (EMIB) and magnetic inductor structures within coreless organic semiconductor packages, where EMIBs enhance I/O density and magnetic inductors improve power delivery efficiency, while minimizing exposure to wet chemistries by encapsulating copper traces within magnetic material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If tighter line spacing is used to increase I/O density, then I/O density improves, but bump pitch becomes too tight which is less desirable for manufacturing
Solution Approach 1:
The patent introduces EMIB (embedded multi-die interconnect bridge) structures that add a vertical dimension to interconnect architecture. By stacking interconnect layers and using through-silicon vias, the design achieves higher I/O density without reducing the horizontal bump pitch, thus resolving the contradiction between density and manufacturability
Solution Approach 2:
The EMIB structure embeds multiple interconnect bridges within the substrate thickness, nesting multiple connection paths in a compact volume. This allows increased I/O capacity without increasing the footprint or reducing bump pitch, addressing both density and manufacturing constraints
2Use of energy by moving object
If magnetic inductor material is used to improve power delivery efficiency, then power delivery performance improves, but exposure to wet chemistries causes resin bleed out and metallization issues
Solution Approach 1:
The patent applies a protective coating or encapsulation layer over the magnetic inductor material before wet chemistry processing steps. This preliminary protective action prevents resin bleed-out and metallization contamination from affecting the magnetic material during manufacturing, thus maintaining both power delivery efficiency and reliability
Solution Approach 2:
An intermediary protective layer is introduced between the magnetic inductor material and the wet chemistry environment. This mediator layer allows the manufacturing process to proceed while isolating the magnetic material from harmful chemistries, preserving both electrical performance and structural integrity
3Productivity
If coreless packaging is used to reduce z-height and increase throughput, then productivity improves, but I/O density is limited by first level interconnect configurations
Solution Approach 1:
The patent employs multi-layer interconnect structures with vertical stacking of signal paths and through-silicon vias. This vertical dimensionality enables high I/O density in a thin profile, maintaining the productivity benefits of coreless packaging while achieving the required I/O capacity
Solution Approach 2:
Multiple interconnect bridges are nested within the substrate layers, creating a compact three-dimensional interconnect architecture. This nesting approach maximizes I/O density within the limited z-height of coreless packages, achieving both high productivity and high I/O capacity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases I/O density and power delivery performance while minimizing exposure to wet chemistry issues, resulting in more efficient and reliable coreless semiconductor packages with improved throughput.
Implementation Method 1
Power delivery efficiency can be increased by use of magnetic inductor material, which improves the total inductance of the package
Data Source
AI summary
A coreless semiconductor package comprises a plurality of horizontal layers of dielectric material. A magnetic inductor is situated at least partly in a first group of the plurality of layers. A plated laser stop is formed to protect the magnetic inductor against subsequent acidic processes. An EMIB is situated above the magnetic inductor within a second group of the plurality of layers. Vias and interconnections are configured within the horizontal layers to connect a die of the EMIB to other circuitry. A first level interconnect is formed on the top side of the package to connect to the interconnections. BGA pockets and BGA pads are formed on the bottom side of the package. In a second embodiment a polymer film is used as additional protection against subsequent acidic processes. The magnetic inductor comprises a plurality of copper traces encapsulated in magnetic material.


