Coreless Electronic Package Fabrication via Silicon Interposer
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Solution Overview
Problem
Conventional semiconductor packages face challenges in miniaturization due to the need for thick silicon interposers and packaging substrates with core layers, which increase fabrication costs and hinder size reduction, especially when dealing with high I/O count and fine pitch semiconductor chips.
Innovation Solution
The electronic package design eliminates the need for a packaging substrate with a core layer by directly disposing high I/O functionality electronic elements on circuit structures on both sides of the package, using a first and second circuit structure with encapsulants to reduce thickness and area, and forming conductive elements and metal layers for exposure and electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a packaging substrate with core layer is used, then electrical connectivity and structural support are achieved, but package thickness and area increase
Solution Approach 1:
The patent removes the core layer from the packaging substrate, extracting only the necessary functions (electrical connectivity through redistribution layers and structural support through the substrate itself). This eliminates the thick glass fiber core while maintaining essential connectivity functions through alternative pathways.
Solution Approach 2:
The patent transitions from a traditional planar substrate architecture to a three-dimensional stacked architecture using silicon interposers with TSVs. Electrical connectivity is achieved through vertical TSV pathways rather than horizontal routing through a thick core layer, reducing the horizontal area while maintaining connectivity.
2Reliability
If silicon interposer with TSVs is used for high I/O count chips, then electrical connectivity is improved, but fabrication cost and time increase
Solution Approach 1:
The patent performs preliminary actions by pre-forming TSVs and redistribution layers on the silicon interposer before chip mounting. This allows the interposer to be prepared in advance with all necessary electrical pathways established, reducing on-site fabrication time and complexity during final assembly.
Solution Approach 2:
The silicon interposer serves multiple functions simultaneously: it provides mechanical support, establishes electrical connectivity through TSVs, enables signal redistribution, and facilitates thermal management. This multi-functionality consolidates what would otherwise require separate components and processes.
3Reliability
If silicon interposer with TSVs is used for high I/O count chips, then electrical connectivity is improved, but fabrication cost increases
Solution Approach 1:
The patent merges the functions of the packaging substrate, interposer, and TSV structure into a single integrated silicon interposer component. This consolidation eliminates the need for separate packaging substrates with core layers, reducing material costs, assembly steps, and overall manufacturing complexity.
Solution Approach 2:
The patent changes the material parameter from organic packaging substrate with glass fiber core to inorganic silicon interposer. This material substitution enables TSV formation through standard semiconductor processing techniques, reducing fabrication costs compared to forming similar structures in traditional packaging substrates.
4Reliability
If area of silicon interposer and packaging substrate is increased for fine pitch chips, then electrical connectivity is improved, but package miniaturization is hindered
Solution Approach 1:
The patent utilizes vertical dimension through TSVs to achieve electrical connectivity between layers, reducing the need for horizontal routing space. This three-dimensional interconnection approach allows high I/O count and fine pitch chips to be connected without proportionally increasing the package footprint.
Solution Approach 2:
The patent implements a nested structure where the silicon interposer with TSVs is embedded within the overall package structure, and the chip is mounted on top of the interposer. This nested arrangement maximizes space utilization and reduces the total package area while maintaining all necessary electrical connections.
Data Source
AI summary
An electronic package is provided, which includes: a first circuit structure; a plurality of first electronic elements disposed on a surface of the first circuit structure; at least a first conductive element formed on the surface of the first circuit structure; and a first encapsulant formed on the surface of the first circuit structure and encapsulating the first electronic elements and the first conductive element, with a portion of the first conductive element exposed from the first encapsulant. By directly disposing the electronic elements having high I/O functionality on the circuit structure, the present disclosure eliminates the need of a packaging substrate having a core layer, thereby reducing the thickness of the electronic package. The present disclosure further provides a method for fabricating the electronic package.