Ultra-Thin Coreless Semiconductor Package Structure Against SMT Warpage
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Solution Overview
Problem
Conventional semiconductor packages, particularly coreless substrates, suffer from warpage issues during Surface Mount Technology (SMT) processes due to differences in thermal expansion coefficients of materials, leading to manufacturing problems and reduced performance.
Innovation Solution
The development of ultra-thin, hyper-density semiconductor packages using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array metallurgy, combined with metal pillars and pitch translation interposers, minimizes warpage by maintaining precise alignment and structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If coreless substrate technology is used to reduce thickness, then the z-height is reduced, but warpage susceptibility increases during SMT processes
Solution Approach 1:
The patent employs a composite substrate structure combining multiple materials with complementary properties: a flexible circuit board layer provides bendability while a rigid support layer maintains dimensional stability. This composite construction enables the substrate to achieve both reduced thickness and resistance to warpage during SMT processes by distributing thermal stresses across materials with matched coefficients of thermal expansion.
Solution Approach 2:
The patent modifies the coefficient of thermal expansion parameter by selecting and combining materials whose CTE values are carefully matched to each other and to the mounted components. This parameter optimization reduces differential thermal expansion during temperature cycling, thereby minimizing warpage in the ultra-thin package structure.
2Length of moving object
If package thickness is reduced for slimmer designs, then device profile is thinner, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The patent introduces a precision alignment structure consisting of registration marks and alignment features embedded in the substrate layers. These intermediary alignment elements serve as reference points during the assembly process, enabling precise positioning of components even in the ultra-thin package where tolerances are extremely tight.
Solution Approach 2:
The patent replaces traditional mechanical alignment methods with optical alignment techniques using laser-based registration systems. This substitution enables sub-micron precision in component placement without requiring complex mechanical adjustment mechanisms, which would add to the package thickness.
3Quantity of substance
If pitch is reduced for higher density, then component spacing is smaller, but warpage occurs more frequently during assembly
Solution Approach 1:
The patent divides the substrate into multiple segmented regions with independent support structures and reinforcement ribs strategically positioned between component arrays. This segmentation provides localized structural support that prevents warpage in high-density areas while maintaining the fine pitch required for high component density.
Solution Approach 2:
The patent addresses the two-dimensional warpage problem by introducing a third dimension through raised support structures and underfill materials that extend vertically between components. This dimensional approach provides additional structural reinforcement without increasing the horizontal pitch, thereby maintaining high density while preventing warpage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in packages with minimal warpage, achieving ultra-thin z-heights and high die-to-package ratios, suitable for handheld and mobile devices, while ensuring reliable assembly and performance.
Implementation Method 1
SMT processes typically involve subjecting package substrates to heating and cooling which in turn create expansion and contraction of the substrate. The difference in coefficient of thermal expansion (CTE) of the various materials forming the substrate results in different rates of expansion and contraction
Data Source
AI summary
Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra-fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die-to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.