Coreless IC Package With Vertical Capacitor For Signal Integrity
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Solution Overview
Problem
Conventional IC packages with cored substrates are unsuitable for high-speed and high-data-demand electronic devices due to their thickness and impedance issues, which affect signal integrity and power delivery, while coreless substrates are prone to warpage and require improved power delivery network design.
Innovation Solution
A coreless substrate IC package with a multilayer structure, including prepreg layers of varying thickness and CTE, and a vertically mounted die-side capacitor with a conductive layer that encapsulates the capacitor and is electrically coupled to its electrode, reducing warpage and enhancing signal integrity and power delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional cored substrate IC packages are used, then structural stability is provided, but the package thickness increases and impedance issues affect signal integrity
Solution Approach 1:
The patent removes the core layer from the substrate structure, transitioning from a cored substrate to a coreless substrate. This extraction eliminates the thick core that caused impedance issues and signal integrity problems, while maintaining structural stability through the remaining substrate layers and support structures.
Solution Approach 2:
The patent redistributes functional elements vertically across multiple thin layers rather than relying on a thick core. By stacking substrate layers, metal traces, vias, and capacitors in a vertical arrangement, the design achieves the required functionality in a reduced z-height dimension while maintaining electrical performance.
2Length of stationary object
If coreless substrate is used to reduce thickness, then package thickness decreases and signal integrity improves, but the substrate becomes prone to warpage
Solution Approach 1:
The patent applies different thicknesses to different prepreg layers (first prepreg layer has different thickness than second prepreg layer) to create localized structural reinforcement. This non-uniform thickness distribution provides targeted support to prevent warpage in critical areas while maintaining overall thinness of the package.
Solution Approach 2:
The patent uses a composite multilayer structure combining substrate layers, prepreg layers with different CTEs, metal traces, and encapsulation materials. This composite construction balances mechanical properties across layers, using materials with different coefficients of thermal expansion to counteract warpage tendencies and provide dimensional stability.
3Reliability
If vertically mounted die-side capacitors are added to improve power delivery, then power integrity improves, but device complexity increases
Solution Approach 1:
The patent combines the capacitor structure with the substrate itself, integrating vertical capacitors directly into the substrate layers. The capacitors are formed using the substrate's metal layers and dielectric materials, merging two previously separate components (substrate and capacitor) into a unified structure, thereby improving power delivery without proportionally increasing complexity.
Solution Approach 2:
The patent nests the capacitor structure within the substrate layers, with capacitor electrodes and dielectric layers embedded between substrate metal traces. This nested arrangement allows the capacitor to be housed within the existing substrate footprint, utilizing the same vertical space for dual purposes (structural substrate and functional capacitor) without significantly increasing overall device complexity.
Data Source
AI summary
Many aspects of an improved IC package are disclosed herein. The improved IC package exhibits low-impedance and high power and signal integrity. The improved IC package comprises an IC die mounted on a multilayer coreless substrate. The thicknesses of prepreg layers of the coreless substrate are specific chosen to minimize warpage and to provide good mechanical performance. Each of the prepreg layers may have different coefficient of thermal expansion (CTE) and/or thickness to enable better control of the coreless substrate mechanical properties. The improved IC package also includes a vertically mounted die side capacitor and a conductive layer formed on the solder resist layer of the substrate. The conductive layer is formed such that it also encapsulates the vertically mounted capacitor while being electrically coupled to one of the capacitor's electrode.