Coreless Packaging Substrate Anti-Warpage Design
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Solution Overview
Problem
The existing coreless packaging substrates suffer from warpage due to uneven residual stress caused by different curing processes on dielectric layers and non-coplanar solder masks, affecting yield and density in semiconductor packaging.
Innovation Solution
A packaging substrate is fabricated with a 'anti-smile' shape by embedding conductive pads and metal bumps in a dielectric layer, using a conductive seedlayer, and forming a built-up structure with flush conductive pads and dielectric layers, which offsets stress and eliminates the need for laser ablation, allowing for simultaneous formation of multiple metal bumps and improving material uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple curing processes are performed on dielectric layers, then the molecular gathering and shrinking become more complete, but uneven residual stress causes warpage
Solution Approach 1:
The patent applies different curing conditions to different dielectric layers based on their specific requirements. The first dielectric layer undergoes multiple curing processes while subsequent layers receive fewer curing cycles, creating localized quality variations that balance overall stress distribution and prevent warpage.
Solution Approach 2:
The patent modifies curing parameters (number of curing cycles, temperature, time) for different dielectric layers. By changing these parameters locally rather than applying uniform curing to all layers, the method achieves complete molecular gathering while maintaining substrate flatness through stress compensation.
2Reliability
If solder masks are applied on both sides of the substrate, then protection and electrical isolation are improved, but non-coplanar surfaces affect subsequent processing and yield
Solution Approach 1:
The patent embeds conductive pads within the dielectric layer rather than placing them on the surface. This moves the conductive elements from a two-dimensional surface problem to a three-dimensional embedded structure, allowing solder masks to be coplanar while maintaining electrical isolation functionality.
Solution Approach 2:
The patent introduces an embedded conductive pad structure as an intermediary between the solder mask and the electrical connection function. This embedded structure allows the solder mask to maintain a flat coplanar surface while still providing the necessary electrical isolation and connection capabilities.
3Manufacturing precision
If laser ablation is used to form metal bumps, then precise positioning is achieved, but process time and complexity increase
Solution Approach 1:
The patent combines the metal bump formation process with the circuit layer fabrication process. Conductive seeds and metal layers are deposited simultaneously with the circuit patterns using the same plating and etching equipment, eliminating the need for separate laser ablation steps while maintaining precise positioning through photolithography alignment.
Solution Approach 2:
The patent replaces the laser ablation process (optical/mechanical system) with electrochemical deposition and photolithography processes. This substitution uses electroplating to form metal bumps with precise positioning controlled by photomask alignment, reducing process time and complexity while maintaining or improving positioning accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in a more flat and stable packaging substrate with increased density and reliability, reduced process time, and improved yield by offsetting stress and enhancing material uniformity, while eliminating the need for laser ablation and green painting.
Implementation Method 1
one curing process needs to be performed whenever one of the dielectric layers 120a to 120d is formed, in order to cure the newly formed and half cured dielectric layers 120a to 120d
Implementation Method 2
forming a conductive seedlayer on the first dielectric layer and the first ends of the first metal bumps; forming a metal layer on the conductive seedlayer
Data Source
AI summary
A packaging substrate includes a first dielectric layer; a plurality of first conductive pads embedded in and exposed from a first surface of the first dielectric layer; a first circuit layer embedded in and exposed from a second surface of the first dielectric layer; a plurality of first metal bumps disposed in the first dielectric layer, each of the first metal bumps having a first end embedded in the first circuit layer and a second end opposing the first end and disposed on one of the first conductive pads, a conductive seedlayer being disposed between the first circuit layer and the first dielectric layer and between the first circuit layer and the first metal bump; a built-up structure disposed on the first circuit layer and the first dielectric layer; and a plurality of second conductive pads disposed on the built-up structure. The packaging substrate has an over-warpage problem improved.