Ultra-Thin Coreless Semiconductor Packaging for Warpage Resistance
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Solution Overview
Problem
Conventional semiconductor packages, especially coreless substrates, suffer from warpage issues during Surface Mount Technology (SMT) processes due to differences in thermal expansion coefficients of materials, leading to manufacturing problems and reduced performance.
Innovation Solution
The development of ultra-thin, hyper-density semiconductor packages using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array metallurgy, along with metal pillars and pitch translation interposers, to minimize warpage and achieve a thin profile with a high die-to-package ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If coreless substrate technology is used to reduce thickness, then the z-height is reduced, but warpage susceptibility increases during SMT processes
Solution Approach 1:
The patent applies parameter changes by carefully controlling the thickness parameters of substrate layers and adding metallization layers with specific thicknesses (e.g., copper foil thickness of 1-5 micrometers) to achieve the desired z-height while maintaining warpage resistance through optimized structural parameters
Solution Approach 2:
The patent uses composite materials by combining the coreless substrate with metallization layers (copper foil, solder bumps, interposer materials) to create a composite structure that provides both the required thin profile and sufficient mechanical stability to resist warpage during SMT processes
2Length of moving object
If package thickness is reduced to achieve ultra-thin profile, then z-height decreases, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The patent achieves ultra-thin profile (z-height < 1mm) by changing the thickness parameters of all substrate layers and uses precise parameter control of metallization layer thickness (1-5 micrometers) and solder bump dimensions to maintain manufacturing precision throughout the fabrication process
Solution Approach 2:
The patent introduces an interposer as an intermediary element between the substrate and components, which helps transfer and distribute mechanical stresses, thereby maintaining manufacturing precision and reducing warpage in the ultra-thin package structure
3Quantity of substance
If die-to-package ratio is increased to improve density, then space utilization improves, but structural stability may be compromised
Solution Approach 1:
The patent achieves high die-to-package ratio (≥0.7) by using composite materials including metallization layers, solder bumps, and interposer structures that provide both the space utilization for high density and the structural stability needed to maintain package integrity
Solution Approach 2:
The patent applies local quality by concentrating the die area relative to the total package area (achieving ≥0.7 ratio) while providing localized structural support through metallization layers and interposers in critical areas to maintain overall structural stability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The packages exhibit minimal warpage and can be fabricated with a z-height of less than 1 mm and a die-to-package ratio of 0.7 or greater, enhancing manufacturing reliability and performance in handheld and mobile devices.
Implementation Method 1
SMT processes typically involve subjecting package substrates to heating and cooling which in turn create expansion and contraction of the substrate. The difference in coefficient of thermal expansion (CTE) of the various materials forming the substrate results in different rates of expansion and contraction
Data Source
AI summary
Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra-fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die-to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.